91 commits

Author	SHA1	Message	Date
JeanRochCoulon	4423feb06a	Rename ZiCondExtEn and FPGA_EN parameters (#1992)	2024-04-02 15:37:58 +02:00
Jalali	ea2ccffa78	Functional coverage : no need for cvxif directed tests (#1969)	2024-03-29 15:41:13 +01:00
CoralieAllioux	de2e254cd4	[Xcelium support] Remove void from DPI definition (#1856)	2024-03-22 17:07:06 +01:00
MarioOpenHWGroup	62bdf11594	Bump core-v-verif d94f0de and fix questa simulator (#1915)	2024-03-21 19:02:41 +01:00
Côme	13dfa744d2	Parametrization step 1 (#1896)	2024-03-06 17:02:55 +01:00
Jalali	9f928e4c12	Exceptions : Add bins for Read-only CSRs (#1885)	2024-03-05 14:17:56 +01:00
Jalali	ce0ab81630	Connect CSRs info from RVFI_CSR in the testbench & update simulation target (#1879)	2024-02-28 16:20:24 +01:00
CoralieAllioux	68f952b44c	Update usage of riscv_instr_gen_tb_top as in other cores: adapt it in corev-dv to import cva6-dependent packages (#1862)	2024-02-23 23:28:10 +01:00
Jalali	9c4a3c37d6	Remove mcountinhibit from csr_test and UVM env (#1863)	2024-02-21 19:13:57 +01:00
CoralieAllioux	965fd914b2	Bugfix/riscv dv cyclic dependency (#1853)	2024-02-20 12:07:21 +01:00
AEzzejjari	5e80c104c9	AXI agent: Connect the the new AXI agent (#1817)	2024-02-18 23:31:44 +01:00
Jalali	3d7e417bce	Functional coverage : Add cross to illegal and exception coverage models (#1839)	2024-02-18 23:30:11 +01:00
MarioOpenHWGroup	c7f0eaf0d8	Bump verif/core-v-verif from fd68dfd to c7d2077 (#1828)	2024-02-13 14:20:21 +01:00
Jalali	3599839d2e	Functional coverage : Fix illegal cover_group sampling (#1825)	2024-02-12 16:16:38 +01:00
Jalali	22e9173b84	Functional coverage : Create Unmapped instruction and exceptions coverage models (#1818)	2024-02-09 11:31:15 +01:00
Jalali	c2d9d4b283	MTVAL : Remove MTVAL CSR from CVA6 UVM environment (#1788)	2024-01-26 16:47:15 +01:00
Jalali	358a73a07d	Enable zcb extension into cva6 UVM env (#1777)	2024-01-24 15:37:18 +00:00
Jalali	4279cc0f6e	Fix CSR coverage model & HVP (#1751)	2024-01-09 11:55:09 +01:00
Anouar	8aca3438ee	Added CSR covegroups for read and write operations, hvp updated accordantly (#1706)	2023-12-21 13:54:20 +01:00
Jalali	ef4971fa87	CVA6-DV : Add Zcmp extension instructions to CORE-DV (#1648)	2023-11-22 23:13:43 +01:00
Jalali	dc2a177a39	Add constraint to generate illegal sfence.vma func7 (#1640)	2023-11-17 18:14:16 +01:00
Jalali	9623d9c642	Fix TODO, using get_instr_name() of origin riscv_instr class (#1633)	2023-11-15 23:59:58 +01:00
Jalali	0bf653a95b	Add more constraints to cover corner cases in CC (#1632)	2023-11-15 23:59:11 +01:00
Jalali	f9c7542e84	Generate Zcb extension instructions (#1617)	2023-11-14 08:18:28 +00:00
Jalali	5e68fc0a3f	Add more unmapped instructions tests with more combinations (#1622)	2023-11-13 11:44:00 +01:00
MarioOpenHWGroup	220f534b6d	Spike Tandem Implementation using VCS simulator (#1561)	2023-11-09 19:29:24 +01:00
Jalali	3c45510934	HOTFIX: Add parenthesis to "inside" constraint in corev-dv (#1610)	2023-11-08 16:59:51 +00:00
Jalali	5a7bbafdab	Add unmapped Instructions tests to improve code coverage (#1608)	2023-11-08 16:08:19 +01:00
Jalali	24a8992611	CVA6-DV : Add ecall instruction into generate tests (#1604)	2023-11-07 18:01:31 +01:00
Jalali	f301d69675	CORE-DV : Remove c.zext.w instruction from rv32zcb & update the zcb generation (#1585)	2023-10-31 22:50:26 +01:00
Jalali	797f0a90c6	Enable ZBA, ZBB, ZBC, ZBS in cva6 env & generated tests (#1587)	2023-10-31 19:55:08 +01:00
Jalali	e2a5250473	Updates to match the latest version of RISCV-DV (#1576)	2023-10-30 14:10:58 +01:00
Jalali	f5ad0ecef5	DIsable Zicond extension (#1537)	2023-10-17 22:18:06 +02:00
Cesar Fuguet	7de1345291	Add the HPDcache as cache subsystem (#1513) ... Add the HPDcache as another alternative for the cache subsystem. The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.	2023-10-16 09:26:20 +02:00
Anouar	f3eaf4abc7	hvp vplan creation and sanity covergroup implementation (#1518)	2023-10-09 22:29:58 +02:00
Jalali	1a452fb90f	CVA6-DV : Add Zcb extension instructions into cva6-dv (#1496)	2023-10-03 16:14:41 +02:00
Jalali	1f8a67a9b5	HOTFIX : Add CUS_ADD custom instruction under the switch cfg (#1479)	2023-09-27 23:15:19 +02:00
Jalali	0f4212eb2e	CVA6-DV : Add unsupported extension instruction for the embedded config (#1472)	2023-09-26 22:04:14 +02:00
Ayoub Jalali	47bcf3cf5f	ZICOND : Add cover-groups dedicated to Zicond extension in cva6 env	2023-09-25 22:27:53 +02:00
Ayoub Jalali	92b505260b	CVA6-DV : Add Zicond instruction to the cva6-dv	2023-09-25 22:27:53 +02:00
Côme Allart	736be43a73	move files to a verif directory	2023-09-07 09:50:50 +02:00