Côme
0cbd894a7a
update port and config docs ( #2363 )
2024-07-12 17:00:36 +02:00
LQUA
f44655809f
Add CV64A6_MMU core in user manual ( #2324 )
2024-07-09 16:49:31 +02:00
AngelaGonzalezMarino
f8914b9237
Mmu user manual ( #2118 )
2024-05-28 17:45:22 +02:00
AEzzejjari
f0deb6104c
axi Specification: Modify the AXI memory interface specification ( #1960 )
2024-05-27 11:52:27 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
Rohan Arshid
b8ca8588cf
Updated Zcmp extension user guide and specification document ( #1930 )
2024-03-15 18:33:01 +01:00
Rohan Arshid
94f6528e1f
[Docs] Add Zcmp Instructions in CVA6 user guide and requirement specifications ( #1927 )
2024-03-13 22:52:44 +01:00
JeanRochCoulon
b3ae6e9362
Revert MMU ( #1890 )
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* Revert "fix vcs simulation errors regarding hypervisor extension code (#1889 )"
This reverts commit 5ff5f164fb#1881 )"
This reverts commit 6a5863e71a#1876 )"
This reverts commit 9fb5db2555
2024-03-05 16:44:40 +01:00
AngelaGonzalezMarino
6a5863e71a
Mmu user manual ( #1881 )
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* user manual update mmu v0
* Include information for hypervisor extension use. Fix issue in satp mode bits.
* Remove old text
2024-03-05 13:50:45 +01:00
JeanRochCoulon
0f2b137984
Populate instruction chapter in CV32A65X Design Document ( #1820 )
2024-02-12 09:58:02 +01:00
Jérôme Quévremont
ef3bb06fbf
Adding configuration-specific CSR doc ( #1766 )
2024-02-09 13:39:48 +01:00
JeanRochCoulon
2708df998d
Rename cva6 ( #1723 )
2024-01-02 12:05:07 +01:00
Jérôme Quévremont
6e79e20cc6
UM: Part number + reshuffled Zb* RV32/RV64 instructions ( #1733 )
2023-12-21 17:23:14 +01:00
Jérôme Quévremont
5716b378da
Integrated Zb* in user manual (index.rst) ( #1728 )
2023-12-20 08:39:10 +01:00
Gull Ahmed
b3139eaae0
update Zb* docs ( #1721 )
2023-12-19 17:46:23 +01:00
Jérôme Quévremont
4103b2ccdc
Changing part number in user manual ( #1718 )
2023-12-18 16:32:30 +01:00
JeanRochCoulon
5e9cb5d64e
Designdoc ( #1713 )
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* rename csr files
* Revisit the design specification skeleton
2023-12-15 14:51:32 +01:00
Florian Zaruba
344c1db4b8
Clarify pmpcfgX on illegal write combination ( fixes #1694 ) ( #1711 )
2023-12-14 15:48:40 +01:00
Jérôme Quévremont
6e41bc8b52
Updated user manual to address several configuration (second pass) ( #1696 )
2023-12-13 10:10:31 +01:00
Jérôme Quévremont
98c776dc2d
Updated user manual to address several configuration (first pass) ( #1685 )
2023-12-13 10:08:40 +01:00
JeanRochCoulon
9952bce6a6
Add embedded csr description and CSR table list ( #1662 )
2023-12-06 09:16:21 +01:00
André Sintzoff
30cf669a32
CSR user manual: add precise trap description ( fix #1217 ) ( #1646 )
2023-11-21 19:05:50 +01:00
Abdul Wadood
9e47cc6947
removed c.zext.w from rv32 spec ( #1563 )
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Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
2023-10-23 14:55:05 +00:00
Abdul Wadood
43c12816f6
[DOCS] Add Zcb Instructions in CVA6 user guide and requirement specification ( #1536 )
2023-10-19 16:22:46 +02:00
Pascal Cotret
f0bd20b78c
fix most of sphinx warnings ( #1509 )
2023-10-08 14:42:57 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
Fatima Saleem
4fb073f91c
[Docs] Adding Zicond in user and requirement specs ( #1444 )
2023-09-18 23:39:26 +02:00
Asim Ahsan
0aec609196
Update programmers view ( #1259 )
2023-08-23 12:33:39 +02:00
Jérôme Quévremont
8813d96995
[Skip CI] CV-X-IF user guide: editorial changes. ( #1331 )
2023-08-23 12:31:08 +02:00
Guillaume Chauvon
a052d4f2d5
Add CVXIF chapter in user's guide ( #1289 )
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Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2023-08-09 15:49:36 +02:00
Mohamed Aziz Frikha
6ce4705ade
Fix the reset value of MISA in user manual ( fix #1048 ) ( #1330 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-08-08 17:54:59 +02:00
Mohamed Aziz Frikha
853fb4bee5
[DOC] Adding legal values to MIP, MIE, SIP and SIE registers ( #1326 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-08-03 09:34:23 +02:00
Mohamed Aziz Frikha
b928fdfade
Adding Legal values to MTVEC and STVEC registers to fix #1060 and #1079 issues ( #1325 )
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* Adding Legal values to MTVEC and STVEC registers to fix #1060 and #1079 issues
* Updating MTVEC and STVEC description
---------
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-31 11:45:00 +02:00
Mohamed Aziz Frikha
716bc7175a
Adding RISC-V behavior (WARL, WLRL, WPRI) to the specification of CSRs ( #1314 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-20 19:09:34 +02:00
André Sintzoff
9b4b6abe61
Traps_Interrupts_Exceptions.rst: update chapter ( #1291 )
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Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-07-20 10:56:09 +02:00
Mohamed Aziz Frikha
5fff2244e4
Adding Fields VS and UBE to MSTATUS in Specification to solve issue #1131 ( #1308 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-19 17:24:12 +02:00
Florian Zaruba
7068948245
Add first draft on PMA region ( #1295 )
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* Add first draft on PMA region
* Address code review comments
2023-07-04 15:28:44 +02:00
Mohamed Aziz Frikha
3cb54a1623
Changing Addresses of ICACHE and DCACHE to solve #1202 issue. ( #1290 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-01 17:27:57 +02:00
Mohamed Aziz Frikha
71e7019834
Adding WPRI in spec : register MSTATUS ( #1257 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-06-08 22:42:04 +02:00
TulikaSi
4e74335884
Update CSR_Performance_Counters.rst ( #1249 )
2023-06-08 07:25:32 +02:00
AEzzejjari
8fec3db665
modifications of the AXI interface specification. ( #1251 )
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Signed-off-by: Alae Eddine Ez zejjari <alae-eddine.ez-zejjari@external.thalesgroup.com>
2023-06-08 07:22:47 +02:00
Jalali
61d5433c4b
ISA SPEC: Update RISCV_Instructions.rst ( #1247 )
2023-05-26 17:19:27 +02:00
Jalali
be58d57de1
ISA SPEC: Fix the c.addi4spn instruction's format ( #1245 )
2023-05-24 13:22:16 +02:00
Mohamed Aziz Frikha
b36703a80e
Add RST and YAML files generated from IP-XACT ( #1221 )
2023-05-03 16:46:16 +02:00
JeanRochCoulon
ca9fd0e41d
Update mscratch description in CSR specification ( #1216 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-05-02 17:39:41 +02:00
JeanRochCoulon
4f06aa620f
Add ip-xact directory to host all relative CSR files ( #1211 )
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As CSR chapter has been moved to User Manual specification, CSR ip-xact is moved too.
Remove XML file duplication, the only referent XML is the 2014 version XML.
2023-04-27 11:54:52 +02:00
Jalali
64da01365a
ISA Spec : Update isa specification ( #1183 )
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Signed-off-by: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
2023-04-19 22:40:20 +02:00
Jérôme Quévremont
d77623b5c6
[Skip CI] Various user's guide edits ( #1201 )
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* Add mention to a single hart core
Mentions CVA6 has a single hart + minor edit.
* Update Custom_Instructions.rst
Minor edit.
2023-04-19 18:33:24 +02:00
Flavien Solt
0c3688ccb8
Fix satp spelling in documentation ( #1199 )
2023-04-19 14:12:25 +02:00
Jérôme Quévremont
ee1560fa38
[Skip CI] Adding the virtual memory section ( #1114 )
2023-04-11 11:00:36 +02:00
