Florian Zaruba
e873743b54
Release 4.2.0
2019-06-04 10:36:17 +02:00
Florian Zaruba
4ca7b6cb67
Fix CHANGELOG.md to point to the right versions
2019-06-04 10:36:17 +02:00
Michael Schaffner
d50a5eb60c
Bump common cells and fpu
2019-06-04 10:36:17 +02:00
Michael Schaffner
7b305dd6c0
Fix run.tcl (moved include path declaration to the beginning)
2019-06-04 10:36:17 +02:00
Michael Schaffner
0292852fae
Fix lint warnings
2019-06-04 10:36:17 +02:00
Michael Schaffner
f96db9af5e
Safeguard memory responses in wt_missunit
2019-06-04 10:36:17 +02:00
Michael Schaffner
c06f6a2a49
Bump axi submodule to v0.7 and fix include path for registers.svh in run.tcl
2019-06-04 10:36:17 +02:00
Michael Schaffner
39e4ebce0b
Fix include path for registers.svh in run.tcl
2019-06-04 10:36:17 +02:00
Michael Schaffner
ba098456a6
Bump axi submodule to v0.6
2019-06-04 10:36:17 +02:00
Michael Schaffner
94c17c8f1c
Update changelog and fix potential bug in install-verilator script
2019-06-04 10:36:17 +02:00
Michael Schaffner
2336f7e2e2
Update changelog
2019-06-04 10:36:17 +02:00
Michael Schaffner
580024accf
Bump FPU submodule
2019-06-04 10:36:17 +02:00
Michael Schaffner
07aeb56387
Update to Verilator 4.014
2019-06-04 10:36:17 +02:00
Jonathan Richard Robert Kimmitt
957ba3adaf
Remove duplicated interface aliases
2019-06-04 10:36:17 +02:00
Michael Schaffner
f2b9a46c21
Update changelog
2019-06-04 10:36:17 +02:00
Michael Schaffner
e46bb157fa
This replaces the axi-lite-apb64to32 converter chain with a simpler shim in order to fix issues with unaligned accesses to the PLIC (only relevant for OpenPiton+Ariane)
2019-06-04 10:36:17 +02:00
Michael Schaffner
416aec8986
Bump FPU, DM and common cells
2019-06-04 10:36:17 +02:00
Michael Schaffner
fca6a7738c
Add ifndef VERILATOR in instruction tracer files
2019-06-04 10:36:17 +02:00
Michael Schaffner
45762c7c67
Remove IRQ sync regs as they are not needed for openpiton
2019-06-04 10:36:17 +02:00
zachzzc
47fe4d35e4
travis: Split into smaller travis tests
2019-06-04 10:36:17 +02:00
Michael Schaffner
276d0c144c
Make interrupt sensitivity configurable in openpiton periphs, add sync stage
2019-06-04 10:36:17 +02:00
Michael Schaffner
5edf35804f
Bump FPU submodule
2019-06-04 10:36:17 +02:00
Michael Schaffner
b1b22db39a
Bump common cells
2019-06-04 10:36:17 +02:00
Michael Schaffner
1c4940f4cd
Scoreboard refactoring for better timing
2019-06-04 10:36:17 +02:00
jrrk
2f0d26d997
bht: Prevent array from overflowing ( #244 )
2019-06-04 10:36:17 +02:00
Florian Zaruba
1b5caa3b9a
instr_queue: Fix latch in fetch_entry_o
2019-06-04 10:36:17 +02:00
Florian Zaruba
11c36cb5d3
bender: Use Bender to generate file lists
2019-06-04 10:36:17 +02:00
Florian Zaruba
a868829d57
synthesis: Fix problems with Synopsys DC
2019-06-04 10:36:17 +02:00
Florian Zaruba
93e27812c7
csr_file: Fix propper setting of sd flag
2019-06-04 10:36:17 +02:00
Jonathan Richard Robert Kimmitt
3d09828552
Add pragma around non-synthesisable code
2019-06-04 10:36:17 +02:00
Florian Zaruba
405ba6c3c3
fp_dirty: Dirty on fp register write
2019-06-04 10:36:17 +02:00
zachzzc
62327627a5
testHarness: Fix the multi-thread library dependency error
2019-06-04 10:36:17 +02:00
Stefan Mach
a44550af4f
🐛 Fix F2I bug in FPU
2019-06-04 10:36:17 +02:00
Stefan Mach
44d01c0911
⬆️ Update FPU for better conversion pipe
2019-06-04 10:36:17 +02:00
msfschaffner
c02597c2ff
fpu: Bump submodule ( #232 )
2019-06-04 10:36:17 +02:00
Florian Zaruba
fbb4fad807
fpu: Proper dirty FP state ( fix #229 )
2019-06-04 10:36:17 +02:00
Florian Zaruba
879b1c2ca7
fpga: Remove default_nettype for Vivado 2018.3
2019-06-04 10:36:17 +02:00
Florian Zaruba
830540b757
frontend: Clean-up instruction frontend
...
The instuction frontend has become an increasingly messy part an needed
cleaning-up. The current solution contains 2 x 32 bit instruction data
fifos and 1 x 64 bit address fifo. Hence, it should be significantly
more area efficient that the previous one. The interface to `id_stage`
is a ready/valid handshake. The credit based system has been replaced in
favour of a replay mechanism as it was very brittle and overly
pessimistic.
Branch-prediction has been cleaned up: The front-end was also partially
predicting on jumps, this could have potentially let to performance bugs
if the branch detection wasn't correct in the frontend.
2019-06-04 10:36:17 +02:00
Florian Zaruba
90b76d3e4f
tandem: Fix exception detection
2019-06-04 10:36:17 +02:00
Florian Zaruba
6902d2e53b
btb: Remove clear flag
...
In anticipation of cleaning up the branch-prediction a clear flag is no
longer needed. We know at prediction time whether the instruction is a
branch or not. This makes the effect of aliasing very unlikely.
2019-06-04 10:36:17 +02:00
Florian Zaruba
1ebca456ad
ariane: Replace branchpredict_t with bp_resolve_t
...
The new name better captures the meaning of the signal.
2019-06-04 10:36:17 +02:00
Florian Zaruba
13a9767dfe
ras: Handle simultaneous push and pop
2019-06-04 10:36:17 +02:00
Michael Schaffner
95e099ca6f
common_cells: Bump and remove deprecated modules
2019-06-04 10:36:17 +02:00
Michael Schaffner
d30369da8a
fpu: Add distributed pipe regs to ease FPGA timing
2019-06-04 10:36:17 +02:00
Florian Zaruba
43d8bf3765
commit_log: Align compressed encoding to Spike
2019-06-04 10:36:17 +02:00
Florian Zaruba
e312b226de
instruction_tracer: Fix compressed tracing ( fix #134 )
...
The built-in tracer now supports tracing compressed instructions. The
Spike commit log feature has been adapted and is now a 100% aligned.
2019-06-04 10:36:17 +02:00
Michael Schaffner
720910dad0
🎨 Beautify
2019-06-04 10:36:17 +02:00
Michael Schaffner
3a9d4e0f2c
Add missing instruction tracer file
2019-06-04 10:36:17 +02:00
Michael Schaffner
c1fc73c326
Bump common cells
2019-06-04 10:36:17 +02:00
Michael Schaffner
b8ce24c3ab
Rework performance counters such that VCS is happy
2019-06-04 10:36:17 +02:00
