AEzzejjari
c67fdff8db
Condition the compressed decoder with the FpPresent parameter ( #1605 )
2023-11-08 12:28:03 +01:00
Jalali
24a8992611
CVA6-DV : Add ecall instruction into generate tests ( #1604 )
2023-11-07 18:01:31 +01:00
AEzzejjari
2c4d8b3e11
Code coverage: Add SMODE parameter to the sfence_vma instruction ( #1603 )
2023-11-07 15:35:06 +01:00
Jalali
c31ebcd321
Add CSRs tests for embedded config ( #1601 )
2023-11-07 14:09:08 +01:00
Côme
168292364a
use embedded config to run coremark ( #1602 )
2023-11-07 14:06:10 +01:00
dependabot[bot]
08b7a9d428
Bump verif/core-v-verif from 717d05e to a687a60 ( #1600 )
2023-11-06 20:45:23 +01:00
JeanRochCoulon
d087fd7c8a
[HOT FIX] Add else to SRET instruction decode ( #1595 )
...
Add the generation of illegal instruction in case of SRET decoding and supervisor mode disable
2023-11-06 08:21:12 +00:00
JeanRochCoulon
3fcb7b9c9b
Do not support DRET when DebugEn = 0 ( #1596 )
...
When debug mode is disable, DRET instruction is not supported.
2023-11-06 07:50:46 +00:00
JeanRochCoulon
b7e936e754
Implement only 1 dcache_ctrl instances when ACC and MMU_PRESENT are disabled ( #1594 )
2023-11-05 23:37:42 +01:00
Côme
b2a59c9617
Convert DV into a submodule ( #1591 )
2023-11-03 11:20:08 +01:00
JeanRochCoulon
b6ff6887c7
[hot fix] Update expected gate count ( #1590 )
2023-11-03 08:06:51 +00:00
Fatima Saleem
f14254dff6
removing zexth duplicated code for RV64 ( #1589 )
...
revert decoder.sv modifications done in a99f115d41
2023-11-02 09:29:47 +00:00
Jalali
f301d69675
CORE-DV : Remove c.zext.w instruction from rv32zcb & update the zcb generation ( #1585 )
2023-10-31 22:50:26 +01:00
Jalali
797f0a90c6
Enable ZBA, ZBB, ZBC, ZBS in cva6 env & generated tests ( #1587 )
2023-10-31 19:55:08 +01:00
Fatima Saleem
a99f115d41
conditioned RTL with XLEN parameter ( #1579 )
2023-10-31 19:54:19 +01:00
AEzzejjari
1faaec09bc
Code_coverage: condition RTL with the debug parameter ( #1582 )
2023-10-31 17:35:59 +01:00
Jérôme Quévremont
a34aca924e
Add funding acknowledgement ( #1581 )
2023-10-31 17:12:32 +01:00
AEzzejjari
d92f0f76d0
Code_coverage: condition RTL with the U-MODE parameter ( #1583 )
2023-10-31 13:45:58 +01:00
JeanRochCoulon
18e9d8ea8e
Reduce the number of executed tests ( #1580 )
...
As the execution of this job is longer than other jobs, reduce the number of executed jobs.
2023-10-31 09:36:28 +01:00
JeanRochCoulon
73a6b84e11
Generate illegal exception when accessing CSR Trigger CSRs ( #1577 )
...
CSR_TSELECT, CSR_TDATA1, CSR_TDATA2, CSR_TDATA3 are not implemented yet. Gen exception when accessing these CSRs.
2023-10-30 17:08:15 +01:00
Jalali
e2a5250473
Updates to match the latest version of RISCV-DV ( #1576 )
2023-10-30 14:10:58 +01:00
AEzzejjari
4b67475fa4
Code_coverage: condition RTL with the S-MODE parameter ( #1574 )
2023-10-27 22:38:52 +02:00
JeanRochCoulon
53d388071d
Condition dcache_ctrl by MMU_PRESENT ( #1568 )
...
When MMU is not present ldst does not request address translation, that's why related dcache_ctrl is not useful. Condition it to MMU_PRESENT to increase code coverage and decrease the gate count.
2023-10-24 17:29:47 +02:00
dependabot[bot]
b9d1a2ecf1
Bump verif/core-v-verif from 91b01d2 to 717d05e ( #1567 )
2023-10-24 04:35:12 +02:00
Saad Waheed
584198427b
[CI] Update Verilator version to v5.008 ( #1566 )
...
Signed-off-by: Saad Waheed <saad.waheed@10xengineers.ai>
2023-10-23 22:38:17 +02:00
Abdul Wadood
9e47cc6947
removed c.zext.w from rv32 spec ( #1563 )
...
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
2023-10-23 14:55:05 +00:00
Fatima Saleem
38b1da26c3
adding bitmanip and atomic arch-tests ( #1560 )
2023-10-20 16:03:12 +02:00
Fatima Saleem
49a4b5b4ff
resolving lint warnings... ( #1529 )
2023-10-20 15:01:42 +02:00
Florian Zaruba
60dde07761
[license] Fix license headers in FPGA bootrom ( #1556 )
2023-10-20 09:19:41 +02:00
AEzzejjari
29a3f14868
Code_coverage: Add conditions for the AMO Extension ( #1554 )
2023-10-19 22:08:40 +02:00
Luca Colagrande
74675b400c
Support multiple outstanding stores ( #1474 )
2023-10-19 22:03:54 +02:00
Florian Zaruba
9b55204283
[ci] Run stale job on schedule ( #1555 )
2023-10-19 20:20:44 +02:00
Florian Zaruba
04766ee5d7
[bot] Add stale-bot ( #1552 )
2023-10-19 16:32:04 +02:00
Robert Balas
99b1e8fec5
perf_counters: Fix counter resetting to zero ( #1546 )
2023-10-19 16:24:48 +02:00
Côme
588cf6ecf0
ci: enable job status checker in "dev" pipeline ( #1548 )
2023-10-19 16:23:51 +02:00
MarioOpenHWGroup
ac79766e79
Delete remaining files from riscv-isa-sim ( #1549 )
2023-10-19 16:23:07 +02:00
Abdul Wadood
43c12816f6
[DOCS] Add Zcb Instructions in CVA6 user guide and requirement specification ( #1536 )
2023-10-19 16:22:46 +02:00
Côme
d2d178d3a3
ci(dev): run synthesis tests only when RTL has changed ( #1550 )
2023-10-19 12:22:52 +02:00
JeanRochCoulon
d29021ea22
[HOTFIX] Delete vendor/patches/riscv/riscv-isa-sim directory ( #1545 )
...
Spike has been moved from CVA6 to Core-v-verif repository except the patches. Clean-up to avoid redundancy between repositories.
2023-10-18 20:42:11 +02:00
MarioOpenHWGroup
3e72504d97
Get spike from cvv repo ( #1544 )
...
* Change target on install-spike
* Delete vendor/riscv/riscv-isa-sim
2023-10-18 17:39:40 +02:00
Florian Zaruba
20c6556e4c
tracer: Use hart_id for trace file format ( #1543 )
2023-10-18 17:39:06 +02:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
dependabot[bot]
3d47805dfc
Bump verif/core-v-verif from 580ea6f to 91b01d2 ( #1539 )
2023-10-18 10:52:41 +02:00
Jalali
f5ad0ecef5
DIsable Zicond extension ( #1537 )
2023-10-17 22:18:06 +02:00
Côme
879f84e313
ci: use spike from core-v-verif ( #1538 )
2023-10-17 22:06:15 +02:00
Jalali
03490e43a8
Update tests' description & enable hvp for coverage report ( #1532 )
2023-10-17 22:00:47 +02:00
JeanRochCoulon
fb7064da00
Disable Zicond in cv32a6_embedded_config_pkg.sv ( #1534 )
2023-10-17 17:13:10 +02:00
JeanRochCoulon
f4378ca660
Do not execute "regress" CI on PR ( #1535 )
...
To reduce the CI execution time on servers
2023-10-16 14:06:55 +02:00
Cesar Fuguet
7de1345291
Add the HPDcache as cache subsystem ( #1513 )
...
Add the HPDcache as another alternative for the cache subsystem.
The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.
2023-10-16 09:26:20 +02:00
Florian Zaruba
166c4b8ba1
[config] Reduce number of commit ports to one ( #1531 )
2023-10-13 14:30:18 +02:00
