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Author SHA1 Message Date
Christian Herber
91f500106f Adding some cross references to specifications 2023-08-15 13:33:52 +02:00
Christian Herber
2ad7982ba1 Cleaning up references. Proper citations in place 2023-08-15 11:26:54 +02:00
Christian Herber
fed1a877bc Adding initial version of CV32E20 specification 2023-08-15 10:36:25 +02:00
Christian Herber
5c5aaae1f0 Adding Jinja2 with version restriction to requirements 
- Jinja2 is required by sphinx
- Version 3.1 and later are incompatible with the specified sphinx version
- see https://github.com/sphinx-doc/sphinx/issues/10291
- explicitly requiring this older version of Jinja2 solves this
- could be removed when moving to newer sphinx version
 2023-07-05 17:15:38 +02:00
christian-herber-nxp
a0f5aafc4d
Merge pull request #129 from NXP/bug/por-value-of-mstatus 
fix #128 power-on-reset value for MSTATUS CSR
 2023-06-29 18:04:19 +02:00
Szymon Bieganski
34214541e0
fix #128 power-on-reset value for MSTATUS CSR 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-06-26 15:49:28 +02:00
Davide Schiavone
b8c94a3e84
fix waiver and .sv file for verilator (#123) 2023-06-03 08:47:26 +02:00
Davide Schiavone
06c4a0c0e6
add fetch_enable_i (#118) 
* add fetch_enable_i

* fix missign signals

* removed unused signals
 2023-06-01 14:41:31 +02:00
christian-herber-nxp
3a9f2d058f
Feature/remove writeback stage (#56) 
* remove parameter option WritebackStage

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from examples

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from compliance verification

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from formal verification code generated for SymbioticEDA

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove reference to the deleted parameterd from the documentation
Do not refer to WriteBack as to a stage

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove related code to Writeback stage

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Removal of related and dead code after Writeback-stage removal

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* substitute ASSERT macro with one ignoring rst_ni and clk signals

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* keep clk_i and rst_ni for the sake of assert alone

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* BUGFIX: reintroduce en_wb signal between id and wb

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-05-31 14:44:59 +02:00
Davide Schiavone
cd76f83e12
fix regfile 0 val and sec script (#119) 
* fix sec script

* fix reg fil 0 val
 2023-05-31 14:42:22 +02:00
Davide Schiavone
1253782b42
fix verilator .core (#116) 
* fix top and sec

* fix .core
 2023-05-25 15:36:17 +02:00
Davide Schiavone
0a9e862fee
fix top and sec (#115) 2023-05-25 09:43:54 +02:00
Davide Schiavone
9abe653e1b
fix verilator and add clk gating cell (#114) 
* fix verilator

* add clk gating cell

* remove prim_generic_buf from manifest

* fix comment
 2023-05-24 15:18:26 +02:00
MarioOpenHWGroup
67def6f46e
Add SEC scripts (#113) 2023-05-15 15:03:24 +02:00
MarioOpenHWGroup
f20fc8bcc7
IF: Rename instr_is_compressed_out to fix compilation (#112) 2023-05-10 15:51:51 +02:00
Mike Thompson
6bb99ef52e
Merge pull request #18 from DBees/UpdateIssuesTemplates 
This replaces the Ibex markdown issues templates with YAML issues tem…
 2023-03-24 09:25:47 -04:00
DBees
4c629bf006 Remove check boxes 2023-03-23 15:21:17 -07:00
christian-herber-nxp
685f1f6ee7
Feature/privil mode spec update (#96) 
* [rtl] Clear mprv on mret to non M-mode

This is specification change between the v1.11 and v1.12 privileged
architectures. Previously mprv wasn't altered on mret. Now if returning
to a privilege level other than M mode mprv must be cleared.

* [rtl, dv] Add new CSRs for latest priviledged spec

This adds the following CSRs to support the v1.12 priviledged spec.

 - MSTATUSH
 - MCONFIGPTR
 - MENVCFG
 - MENVCFGH

MCONFIGPTR is read only and has its value provided by a ibex_pkg
parameter CSR_MCONFIGPTR_VALUE which is set to 0. Implementors can alter
this value if needed.

All the other CSRs ignore writes and read as 0.

---------

Co-authored-by: Greg Chadwick <gac@lowrisc.org>
 2023-03-03 17:18:30 +01:00
christian-herber-nxp
823f596047
Relocate RegFile from TOP level to CORE level (#95) 
Remove dead and related code

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-03-03 17:09:12 +01:00
christian-herber-nxp
ec096aafd3
[rtl] Don't take interrupts when single stepping (#97) 
Fixes #1814

Co-authored-by: Greg Chadwick <gac@lowrisc.org>
 2023-03-03 17:06:49 +01:00
christian-herber-nxp
f6268d4eb9
[rtl] Remove unused transition in ibex_controller FSM (#98) 
When in the FLUSH state we cannot have `csr_pipe_flush` set as it
depends upon `instr_executing` being set (within `ibex_id_stage`) and
that is only set in the DECODE stage.

Co-authored-by: Greg Chadwick <gac@lowrisc.org>
 2023-03-03 17:06:24 +01:00
christian-herber-nxp
91eb8564de
Feature/flush ctrl in csrwrite (#99) 
* [rtl] Flush controller in PMP CSR write ops

As Greg pointed out:

When we have an instruction in ID/EX that writes a PMP register that
update gets written to the CSR the same cycle the next instruction
moves from IF to ID/EX with it's PMP check done with the old value.

The solution is to flush the pipeline when we get a PMP CSR write.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

* [rtl] Flush pipe on MSECCFG CSR write

Without this an instruction executed immediately after the MSECCFG write
doesn't have the new MSECCFG setup applied to its execute permission.

---------

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Co-authored-by: Canberk Topal <ctopal@lowrisc.org>
Co-authored-by: Greg Chadwick <gac@lowrisc.org>
 2023-03-03 17:05:51 +01:00
christian-herber-nxp
d6f0e2ccff
Feature/remove security (#52) 
* Remove ResetAll parameter

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove ICache and related paramters

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove reference to the deleted parameterd from the documentation

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to the removed parameters from the example configurations

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove security features, and related code

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove complete security section from Reference documentation sub-page

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to deleted security features

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove reference to the removed dummy_instr.sv

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove Lockstep

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove DummyInstruction related code

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to SecureIbex in documentation

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove related and dead code to security features

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove Security option from example configurations

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove security related signals and CSR register

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-28 14:03:42 +01:00
christian-herber-nxp
2aa3bf8b2d
Keep bit-manipulation extension control option as localparam (#55) 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-14 13:59:22 +01:00
christian-herber-nxp
e7559f327d
Feature/remove branch target alu (#51) 
* remove BranchTargetALU param.

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from the documentation

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from the example configurations

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from examples

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from compliance verification

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from core lists

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to the removed parameter(s) from Yosys framework configuration parser

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-13 18:59:56 +01:00
christian-herber-nxp
7a678a54c4
Remove parameter RegFileDataWidth (#50) 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-13 18:56:49 +01:00
christian-herber-nxp
483e91daea
Feature/use wfi cycles for mhpmcounter11 (#23) 
* create perf_wfi_wait_o signal

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* connect wfi_o to core

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* use perf_wfi signal to increment mhpmcounter[11]

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* complete documentation with modified function of mhpmcounter[11]

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* closes #17 Repurpose performance counter for mul_wait
fix: remove spurious output signal of perf_mul_wait_o

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-13 18:51:04 +01:00
christian-herber-nxp
1bed05ca43
Keep DbgTriggerEn and DbHwBreakNum as local params (#47) 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-07 13:01:51 +01:00
christian-herber-nxp
c40138f0ef
Keep Physical Memory Protection as local parameter (#48) 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-02-06 14:03:02 +01:00
christian-herber-nxp
ffa6ab4154
Fixing dark mode visibility of block diagram by adding background to boxes where missing (#27) 
Signed-off-by: Christian Herber <christian.herber@oss.nxp.com>

Signed-off-by: Christian Herber <christian.herber@oss.nxp.com>
 2023-01-17 14:58:02 +01:00
christian-herber-nxp
70c2b894f2
Fixes #28: remove references to deleted files (#29) 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-01-17 14:57:27 +01:00
christian-herber-nxp
932db14619
Rename all modules to cve2 (#25) 
* rename files and modules to cve2

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* updated tb files

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remaining references to ibex: gitignore, examples, etc.

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2023-01-05 10:27:24 +01:00
Mike Thompson
bbe47ea66b
Merge pull request #24 from NXP/feature/rework-readme 
Feature/rework readme
 2023-01-04 10:11:27 -05:00
Christian Herber
81f9162752 Clean up of incorrect references 
Signed-off-by: Christian Herber <christian.herber@oss.nxp.com>
 2023-01-04 13:48:43 +01:00
Christian Herber
5cd0623715 Fixed references in CONTRIBUTING.md 
Signed-off-by: Christian Herber <christian.herber@oss.nxp.com>
 2023-01-04 13:45:23 +01:00
Mike Thompson
a5732a66c0
Merge pull request #26 from NXP/feature/dv_cleanup 
clean design verification [dv] folder
 2022-12-21 12:20:06 -05:00
Szymon Bieganski
3834421ba5 closes #21 : clean design verification [dv] folder 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
 2022-11-22 14:07:44 +01:00
Davide Schiavone
321b83303c
update block diagram (#20) 2022-11-14 15:00:59 +01:00
Christian Herber
2d7bb4aea5 Updated contributing guidelines to adjust for change from lowRISC to OpenHW Group 
Signed-off-by: Christian Herber <christian.herber@oss.nxp.com>
 2022-11-14 10:41:33 +01:00
Christian Herber
d28bdcc983 Updated Readme to reflect changes from Ibex to CVE2 
Signed-off-by: Christian Herber <christian.herber@oss.nxp.com>
 2022-11-14 10:40:58 +01:00
DBees
49dc00fe96 This replaces the Ibex markdown issues templates with YAML issues template based on CVA6 2022-11-07 15:23:00 -08:00
Mike Thompson
520888bedf
Merge pull request #16 from MikeOpenHWGroup/main 
Working manifest (temporary solution for simulation)
 2022-10-14 13:33:40 -04:00
Mike Thompson
0f6177baea Working manifest (temporary solution for simulation) 
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
 2022-09-19 20:05:10 -04:00
Davide Schiavone
2ea28638f0
Merge pull request #1 from davideschiavone/remove_legacy_80 
removed legacy 0x80 offset from bootaddr
 2022-07-01 18:30:02 +02:00
Davide Schiavone
be70b262f6 removed legacy 0x80 offset from bootaddr 2022-06-30 08:41:35 +02:00
Davide Schiavone
e082ef9188
Update README.md 2022-04-22 09:46:08 +02:00
Rupert Swarbrick
2f1e188346 Fix port list in top_artya7 example 
The "alert_major" port was split into "internal" and "bus" parts back
in commit 9943f9a. Update the example to match.
 2022-03-15 15:37:03 +00:00
Greg Chadwick
094451a948 [doc] Add examples info to README 2022-03-11 17:28:52 +00:00
Prajwala Puttappa
0a8b4a4f61 [icache, dv] Made changes required to make TB compatible with Xcelium 2022-03-10 14:18:50 +00:00
Prajwala Puttappa
15da12dfd6 Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
7c4f8b3fde4bb625ac3330ff52d3f66507190fe5

* Revert "[dv] Allow using memutil_dpi_scrambled even without
  prim_ram_1p_scr" (Rupert Swarbrick)
* [dv] Fix some signed/unsigned comparison warnings (Rupert Swarbrick)
* [dv] Make an implicit up-conversion explicit (Rupert Swarbrick)
* [dv] Remove an unused array variable in prince_ref.h (Rupert
  Swarbrick)
* [prim/security] Improve the code for prim_sparse_fsm security check
  (Cindy Chen)
* [dv] Apply VCS option `-xprop=mmsopt` only when wave dump is off
  (Weicai Yang)
* [all] variety of minor lint fixes (Timothy Chen)
* [dv] Add options to improve VCS runtime (Weicai Yang)
* [rv_dm] CSR test fixes (Srikrishna Iyer)
* [dvsim] Fix pass/fail status for synthesis regression (Michael
  Schaffner)
* [prim] Minor lint fixes for unused clocks / resets (Timothy Chen)
* [dv] Flag illegal ENUMASSIGN warnings as errors (Michael Schaffner)
* [flash_ctrl] Correct erase suspend interface behavior (Timothy Chen)
* [rstmgr] Address several d2s review items (Timothy Chen)
* [fpv/sec] Add some workaround logic for $cast keyword (Cindy Chen)
* [dv] CSR seq lib - support for adapter-less RAL (Srikrishna Iyer)
* [dv] Prepare codebase for UVM REG changes (Srikrishna Iyer)
* [dv] Print computed CSR stuff in RAL (Srikrishna Iyer)
* [dv] Allow CSR tests to run on custom RALs (Srikrishna Iyer)
* [fpv/rom_ctrl] Check connectivity for alerts in rom_ctrl (Cindy
  Chen)
* [prim] Add prim_and2 primitive (Pirmin Vogel)
* [prim_dom_and_2share] Remove EnNegedge parameter (Pirmin Vogel)
* [prim_dom_and_2share] Use prim_xor2 and prim_flop_en primitives
  (Pirmin Vogel)
* [prim_dom_and_2share] Switch to single randomness input (Pirmin
  Vogel)
* [util/dvsim] Fix confusing error message (Guillermo Maturana)
* [dvsim] Minor changes to SynCfg results reporting (Michael
  Schaffner)
* [fpv] V2S formal support (Cindy Chen)
* [tools/xcelium] updated common coverage exclusions to exclude single
  bit correctly (Rasmus Madsen)
* [dv] Clean up enable_reg_testplan (Weicai Yang)
* [top] Hook-up flash/otp control and observation bus to ast (Timothy
  Chen)
* [lint] Increase the unroll count (Eunchan Kim)
* [entropy_src] Document & Implement THRESHOLD_SCOPE (Martin Lueker-
  Boden)
* [AST] USB Observe, Clocks & POR_NI logic update (Jacob Levy)
* [prim] Add new assertion macro for generating static lint errors
  (Pirmin Vogel)
* [dv] csr_seq_lib fixes (Srikrishna Iyer)
* [dv] dv_base_reg_block - Add special knobs (Srikrishna Iyer)
* [dv] dv_base_mem - add special knobs (Srikrishna Iyer)
* [prim] Move sec_cm assertion to an include file in prim_assert
  (Weicai Yang)
* [flash_ctrl] Fixes for erase suspend (Timothy Chen)
* [dv] exclude d_user.rsp_intg[6] for xcelium (Weicai Yang)
* [prim_flop_en] Dependency fix (Michael Schaffner)
* [dv] add mubi coverage for CSR and update reggen (Weicai Yang)
* [prim] Add option for secure buffers in prim_mubi (Timothy Chen)
* [prim] Add option for hand instantiated buffers for prim_flop_en
  (Timothy Chen)
* [dv/shadow_reg] Move shadow_reg to V2S (Cindy Chen)
* [prim_count] Updated comments to reflect all changes in
  lowRISC/opentitan#10378 (Michael Tempelmeier)
* [dv] Teach ECC32 flavours of mem_area to write with integrity bits
  (Rupert Swarbrick)
* [dv/shadow_reg] update milestone for shadow reg tests (Cindy Chen)
* [checklists] Update V2S checklists (Srikrishna Iyer)
* [tools/xcelium] updated xcelium flow to vcs for coverage test
  grading (Rasmus Madsen)
* [prim] Add stub flops to remove lint warnings (Timothy Chen)
* [dv] Add automatic covergroup for all regwen CSRs (Weicai Yang)
* [dvsim] Add support for tags in testplan (Srikrishna Iyer)
* [dv] Enable xcelium to include X for toggle coverage (Weicai Yang)
* [dv] Clean up mem_bkdr_util__sram (Weicai Yang)
* [util, testplan] Allow relative testplan imports (Srikrishna Iyer)
* [prim] Add phase output to shadow register primitive (Pirmin Vogel)
* [dv] Add assertion to check double_lfsr err triggers an alert
  (Weicai Yang)
* [dv] Fix foundary failure (Weicai Yang)
* [prim] update prim_count comment (Timothy Chen)
* [prim_flop_2sync] Make the prim a standard non-generated prim
  (Michael Schaffner)
* [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen)
* [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy
  Chen)
* [dv] Add countermeasure verification for double_lfsr (Weicai Yang)
* [dv] Update countermeasure verification (Weicai Yang)
* [doc] Update V2S items (Weicai Yang)
* [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded
  (Michael Schaffner)
* [prim_max_tree/fpv] Add a simple formal testbench (Michael
  Schaffner)
* [prim_max_tree] Create a primitive that calculates maxima (Michael
  Schaffner)
* [dv] CSR / RAL model fixes (Srikrishna Iyer)
* [uvmdvgen] bug fix (Srikrishna Iyer)
* [dv] Fix some Xcelium warnings (Srikrishna Iyer)
* [dv] Disable some benign warnings (Srikrishna Iyer)
* [prim_mubi*_sender] Add option to omit sender flops (Michael
  Schaffner)
* [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer)
* [keymgr] sparsify the data control fsm (Timothy Chen)
* [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner)
* [prim] Update behavior of prim_count (Timothy Chen)
* [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen)
* [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana)
* [sw,tests] SRAM execution test DV integration (Dave Williams)
* [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai
  Yang)
* [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala
  Puttappa)
* [rom_ctrl, dv] Fixes regression failures in
  rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa)
* [dv/chip] Add jtag_csr_rw seq (Cindy Chen)
* [chip dv] Remove xcelium build opt (Srikrishna Iyer)
* [doc] Reorder D2S checklist items (Michael Schaffner)
* [reggen] Add support for validation of RTL CM annotation (Michael
  Schaffner)
* [all] various simple lint fixes (Timothy Chen)
* [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert
  Swarbrick)
* [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen)
* [clkmgr] various spec and parameter updates (Timothy Chen)
* [dv] Add ASSERT_NET to check net value (Weicai Yang)
* [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934
  (Weicai Yang)
* [primgen] Update AscentLint waiver in generated abstract prim
  wrappers (Pirmin Vogel)
* [prim_generic] Fix lint errors (Pirmin Vogel)
* [prim_count] Fix lint warnings (Pirmin Vogel)
* [prim_alert_receiver] Fix ping during init sequence bug (Michael
  Schaffner)
* [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa)
* [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer)
* [prim_filter_cnt] Make threshold runtime programmable (Michael
  Schaffner)
* [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter*
  (Michael Schaffner)
* [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to
  V2S (Weicai Yang)
* [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel)
* [sram/dv] Enable the integrity test for passthru (Weicai Yang)
* [dv] Add integrity test for passthru mem (Weicai Yang)
* [dv/tools] Fix alert ping exclusion (Cindy Chen)
* [dv/mem_bkdr_util] added backdoor write of LC counter into LC
  partition in OTP (Dror Kabely)
* [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner)
* [prim_clock_mux] Model generic mux with boolean ops (Michael
  Schaffner)
* [prim_buf] Ensure generic primitives contain a logic cell (Michael
  Schaffner)
* [prim_count] improved documentation and style (Michael Tempelmeier)
* Revert "[dv] Replace fileset_partner flag with fileset_ast flag"
  (Michael Schaffner)
* [dv] Replace fileset_partner flag with fileset_ast flag (Sharon
  Topaz)
* [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang)
* [dv/prim_alert] Add V3 item to testplan (Cindy Chen)
* [dv/prim_count] Add an assertion to check max count stable (Cindy
  Chen)
* [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick)
* [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ
  (Rupert Swarbrick)
* [doc/checklist] Template fix (Cindy Chen)
* [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert
  Swarbrick)
* [rom/ram/xbar/otbn] Switch end-end bus integrity to inverted ECC
  codes (Michael Schaffner)
* [dv/prim_alert_tb] Modify the seq to ensure alert always sends
  (Cindy Chen)
* [dv,xcelium] Fix lowRISC/opentitan#4230: Xcelium compile error.
  (Timothy Trippel)
* [dv/prim_alert] Add randomization in ping request sequence (Cindy
  Chen)
* [prim_alert_receiver] Only check for ping requests after
  initialization (Michael Schaffner)
* [doc] Update D2S checklist template and description (Michael
  Schaffner)
* [prim_esc_receiver] Switch to standardized prim_count (Michael
  Schaffner)
* [prim_count] Add option to disable the connection SVA (Michael
  Schaffner)
* [otbn, rtl] Lint fixes (Greg Chadwick)
* [sram/dv] Better support partial write in scb (Weicai Yang)
* [dv/mem_bkdr_util] Fix ECC width error in OTP foundary test (Cindy
  Chen)
* [secded/lint] Fix lint errors (Michael Schaffner)
* [dv/prim_esc] Add more stimulus to reach coverage goal (Cindy Chen)
* [alert_handler] Switch to sparse fsm primitive (Michael Schaffner)
* [prim_sparse_fsm_flop] Add a parameter to disable SVA (Michael
  Schaffner)

Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
 2022-03-10 14:15:03 +00:00