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  • be0247751a resize image Davide Schiavone 2022-11-14 14:37:58 +01:00
  • e23a9f7b1c update block diagram Davide Schiavone 2022-11-14 14:31:47 +01:00
  • 00410c5798 update block diagram Davide Schiavone 2022-11-14 14:27:23 +01:00
  • 928e65d201 Merge branch 'main' of github.com:davideschiavone/cve2 into main Davide Schiavone 2022-11-14 14:01:18 +01:00
  • 2d7bb4aea5 Updated contributing guidelines to adjust for change from lowRISC to OpenHW Group Christian Herber 2022-11-14 10:41:33 +01:00
  • d28bdcc983 Updated Readme to reflect changes from Ibex to CVE2 Christian Herber 2022-11-14 10:40:58 +01:00
  • 49dc00fe96 This replaces the Ibex markdown issues templates with YAML issues template based on CVA6 DBees 2022-11-07 15:23:00 -08:00
  • 520888bedf
         Merge pull request #16 from MikeOpenHWGroup/main Mike Thompson 2022-10-14 13:33:40 -04:00
  • 0f6177baea Working manifest (temporary solution for simulation) Mike Thompson 2022-09-19 20:05:10 -04:00
  • 5039e60cde add missing signal decl Davide Schiavone 2022-08-11 08:56:53 +02:00
  • 0ae2d4d394 fix sleep unit module name Davide Schiavone 2022-08-11 08:55:07 +02:00
  • 83b027dcde updating .core name Davide Schiavone 2022-08-11 08:44:17 +02:00
  • 89ef78a803 commenting fcov macros Davide Schiavone 2022-08-11 08:42:54 +02:00
  • afe6c56771 update .core file Davide Schiavone 2022-08-11 08:38:13 +02:00
  • 4ef05aa062 add internal clock gating Davide Schiavone 2022-08-11 08:32:05 +02:00
  • 2ea28638f0
         Merge pull request #1 from davideschiavone/remove_legacy_80 Davide Schiavone 2022-07-01 18:30:02 +02:00
  • be70b262f6 removed legacy 0x80 offset from bootaddr Davide Schiavone 2022-06-30 08:41:35 +02:00
  • e082ef9188
         Update README.md Davide Schiavone 2022-04-22 09:46:08 +02:00
  • 2f1e188346 Fix port list in top_artya7 example Rupert Swarbrick 2022-03-10 12:45:53 +00:00
  • 094451a948 [doc] Add examples info to README Greg Chadwick 2022-03-10 17:59:51 +00:00
  • 0a8b4a4f61 [icache, dv] Made changes required to make TB compatible with Xcelium Prajwala Puttappa 2022-03-08 16:20:28 +00:00
  • 15da12dfd6 Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd Prajwala Puttappa 2022-03-08 16:02:51 +00:00
  • e6eb4fb11d [ibex, dv] Added a sequence to toggle fetch_enable_i pin Prajwala Puttappa 2022-03-01 10:15:17 +00:00
  • 3438b77921 [rtl] Add minor alert for icache ECC error Greg Chadwick 2022-03-08 12:07:30 +00:00
  • f89e721040 [icache, rtl] Fix ECC error indication Greg Chadwick 2022-03-08 12:06:56 +00:00
  • 3e4669f086 [rtl] Add SEC_CM markers for security features Greg Chadwick 2022-01-25 14:57:10 +00:00
  • af0c027867 [ibex, dv] Makes delays between req, gnt and rvalid configurable Prajwala Puttappa 2022-02-24 15:03:11 +00:00
  • 46c397501d [ibex, dv] Added new base, interrupt, debug and mem error sequences Prajwala Puttappa 2022-02-18 12:09:40 +00:00
  • c15f3b8888 [icache] Define some fake DPI functions to simplify linking Rupert Swarbrick 2022-03-02 23:46:26 +00:00
  • bdf2f2b440 [ibex, dv] Added agent configuration for ibex_mem_intf_response_agent Prajwala Puttappa 2022-02-23 16:09:57 +00:00
  • 0f69d4972c [dv] Add X assertions for top-level IO Greg Chadwick 2022-02-24 12:59:21 +00:00
  • 58bc6f27ab [doc] Add details about icache latency to DIT docs Greg Chadwick 2022-02-22 16:55:29 +00:00
  • d3bd063662 [rtl] Add prim_buf for security critical signals Greg Chadwick 2022-02-21 17:54:19 +00:00
  • b18eceba81 [rtl] Switch to multi-bit fetch enable Greg Chadwick 2022-02-17 18:39:07 +00:00
  • 3475b9106c Refer to a specific tag for the ibex-cosim version of Spike Rupert Swarbrick 2022-02-18 12:48:50 +00:00
  • 302bb65161 [doc] Update bitmanip list in integration.rst Rupert Swarbrick 2022-02-17 14:58:39 +00:00
  • 36a9abbf1c Use ifndef to avoid re-declaration warnings in *cosim_dpi.svh Rupert Swarbrick 2022-02-17 15:07:17 +00:00
  • 9f14922382 [dv] Construct ISA string from RTL parameters for cosim tests Rupert Swarbrick 2022-02-17 14:51:51 +00:00
  • 9943f9a42c [rtl, doc] Seperate major alert into internal and bus Greg Chadwick 2022-02-17 13:50:08 +00:00
  • e84e7de53f Fix narrowing conversion warning in cosim_dpi.cc Rupert Swarbrick 2022-02-16 12:57:47 +00:00
  • a46ff07489 [rtl] Fix AscentLint errors Pirmin Vogel 2022-02-15 16:58:20 +01:00
  • 336173b4d9 Re-enable bitmanip tests Rupert Swarbrick 2022-02-15 17:50:34 +00:00
  • bc4bafd8ca [docs] Update description of ISS versions Rupert Swarbrick 2022-02-15 17:49:44 +00:00
  • 6f6cafaa4d [ci] Bump Spike version to get cosim implementation Rupert Swarbrick 2022-02-15 15:50:46 +00:00
  • 5691ef1a45 [ci] Bump RISC-V toolchain version to get bitmanip support Rupert Swarbrick 2022-02-15 13:22:10 +00:00
  • bbc48a0c34 Add srecord as simple_system prerequisite fabian 2022-02-08 18:53:26 -05:00
  • 4482af1789 [doc] Fix inline literal syntax in icache.rst Rupert Swarbrick 2022-02-02 09:50:31 +00:00
  • 4bcc0fae6a [doc] Fix botched table layout Rupert Swarbrick 2022-02-02 09:49:31 +00:00
  • 46b7e07098 [doc] Fix RV32B enum description Rupert Swarbrick 2022-01-27 09:21:51 +00:00
  • 69dfa6f8da [ci] Add missing python3-dev dependency Greg Chadwick 2022-01-26 15:09:07 +00:00
  • c0f67946f2 [rtl,doc] Add double fault detection. Greg Chadwick 2022-01-24 18:46:46 +00:00
  • 97fa5cf280 [rtl,doc] Add customisable PMP reset values Greg Chadwick 2022-01-21 17:10:10 +00:00
  • 7c7e0e6d70 [ibex_tracer] Void cast function calls Srikrishna Iyer 2022-01-19 09:26:28 -08:00
  • 187944c417 [icache] Add RAM Primitives for scrambling Canberk Topal 2021-10-07 18:04:56 +01:00
  • e53b033962 [examples/fpga] Fix memory interface Greg Chadwick 2022-01-13 18:17:30 +00:00
  • 2ec8d7433e [examples/fpga] Use 64 kB memory by default Greg Chadwick 2021-09-10 15:32:11 +01:00
  • dcdd982686 [lint] Lint fix for RndCntLfsrX parameters Greg Chadwick 2021-09-10 15:30:41 +01:00
  • 448191dda2 [rtl] Use prim_flop/clock_mux2 primitives for lockstep reset generation Pirmin Vogel 2022-01-11 10:06:21 +01:00
  • 756610800b [doc] Fix config and expand max-width of docs Greg Chadwick 2022-01-10 17:30:13 +00:00
  • 596b4d7e92 [doc] Add new Ibex testplan Greg Chadwick 2022-01-10 17:29:37 +00:00
  • 8c01488624 [rtl] Document lockstep reset generation mechanism Pirmin Vogel 2022-01-07 14:15:41 +01:00
  • a5c55f132e [dv] Add initial coverage plan Greg Chadwick 2021-05-18 17:28:33 +01:00
  • 410ffd349d [bitmanip, doc] Update info on bitmanip support and area numbers Pirmin Vogel 2021-12-10 22:16:07 +01:00
  • 119ac89130 [syn] Add missing package dependency Pirmin Vogel 2021-12-10 17:58:11 +01:00
  • 36c9f4e569 [rtl] Remove redundant comments in decoder Pirmin Vogel 2021-12-10 17:55:08 +01:00
  • 92a95cac32 [bitmanip] Add new configuration option for OpenTitan Earl Grey Pirmin Vogel 2021-12-10 17:54:23 +01:00
  • a33a91b232 [lint] Fix some AscentLint errors Pirmin Vogel 2021-12-13 10:59:22 +01:00
  • fd1195a148 [dv] Set UVM_VERBOSITY to UVM_LOW Greg Chadwick 2021-12-10 10:31:07 +00:00
  • f1cd3bffc6 [dv] Fix bad reference to instr_req_out Greg Chadwick 2021-12-10 10:01:08 +00:00
  • 72a892d62c [rtl] Move PMP checking to IF stage output Tom Roberts 2021-11-16 16:46:23 +00:00
  • fccdd63992 [rtl] Replace always_ff with always @(posedge .. in FPGA regfile Pirmin Vogel 2021-12-09 16:13:02 +01:00
  • fa3df3b8ee [dv] Fix PMP error handling for icache Greg Chadwick 2021-11-05 11:26:19 +00:00
  • 5e7c2cf00a [dv] Add missing copyright header Greg Chadwick 2021-11-05 11:18:24 +00:00
  • cedabf062a [dv] Add recoverable NMI handling to cosim Greg Chadwick 2021-11-05 11:17:35 +00:00
  • 587dc364e9 [dv] Fix dside memory checking Greg Chadwick 2021-11-05 11:15:58 +00:00
  • 545a034957 [dv] Fix cosim memory size Greg Chadwick 2021-11-05 11:14:35 +00:00
  • 045b5707c1 Update google_riscv-dv to google/riscv-dv@6053014 Michael Schaffner 2021-12-08 12:11:40 -08:00
  • 5350c13ae3 [ibex_top] Use correct ECC codeword for '0 reset in regfile Michael Schaffner 2021-12-07 19:46:39 -08:00
  • 804c538db2 Update lowrisc_ip to lowRISC/opentitan@be1359d27 Michael Schaffner 2021-12-07 19:44:54 -08:00
  • c78acac8cc [rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93) Pirmin Vogel 2021-12-02 21:50:20 +01:00
  • 40dab87448 [rtl, bitmanip] Clarify situation around zext.[bh] pseudo-instructions Pirmin Vogel 2021-11-26 16:40:33 +01:00
  • da85ce5ecf [rtl] Fix typo in comment Pirmin Vogel 2021-11-26 16:24:33 +01:00
  • 16d6f5ea2b [rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0 Pirmin Vogel 2021-11-26 14:23:05 +01:00
  • e765b4dfec [rtl, bitmanip] Align Zbs implementation with draft v.0.93 and v.1.0.0 Pirmin Vogel 2021-11-26 13:02:07 +01:00
  • 71b43a83e2 [rtl, bitmanip] Rename bext/bdep to bcompress/bdecompress Pirmin Vogel 2021-11-26 12:43:34 +01:00
  • d8e50dcc2c Update google_riscv-dv to google/riscv-dv@ea8dd25 Pirmin Vogel 2021-12-03 11:39:28 +01:00
  • 169785d071 [secded] Switch to inverted ECC codes Michael Schaffner 2021-12-01 18:19:15 -08:00
  • 4df2221dee Update lowrisc_ip to lowRISC/opentitan@34ba5e45f Michael Schaffner 2021-12-02 11:34:22 -08:00
  • 53b1732b19 Update lowrisc_ip to lowRISC/opentitan@3a672eb36 Canberk Topal 2021-11-29 11:52:25 +00:00
  • 1bbe27effe [dv/icache] Add missing window reset call Tom Roberts 2021-11-18 15:16:08 +00:00
  • ab4041c439 Move NT branch addr calculation to ID stage Sam Shahrestani 2021-11-13 08:36:42 +11:00
  • b66f199151 Update lowrisc_ip to lowRISC/opentitan@ad629e3e6 Rupert Swarbrick 2021-10-05 12:35:08 +01:00
  • e70add7228 [ci] Add co-simulation testing of CoreMark Greg Chadwick 2021-10-21 16:37:43 +01:00
  • 63ac629d10 [coremark] Add option to coremark build to suppress pcount dump Greg Chadwick 2021-10-21 16:13:35 +01:00
  • c3dd66e9fa [cosim] Update documentation for cosim Greg Chadwick 2021-10-21 16:11:31 +01:00
  • 84d2d6ad3f [cosim] Add Simple System with cosim Greg Chadwick 2021-10-21 16:10:48 +01:00
  • 580ddaad13 [simple_system] Refactor Simple System Greg Chadwick 2021-10-21 16:08:44 +01:00
  • b57cad5387 [dv] Add matched instruction count to cosim Greg Chadwick 2021-10-21 16:05:14 +01:00
  • c10b56ed17 [dv] Adjust cosim include paths Greg Chadwick 2021-10-21 15:49:20 +01:00
  • c35472abb9 [bitmanip][zba] Add support for Zba (address calculation) extension Michael Munday 2021-05-12 14:12:34 +01:00