This test doesn't actually check the performance counters, it just runs
a random instruction test and dumps the performance counters at the end
for some final checking. That checking does not exist. The test is
currently broken as well so just remove it as it adds nothing to the
regression.
Update code from upstream repository https://github.com/google/riscv-
dv to revision c6acc1897429f5245cc89b2ecee2e3eefdefd18d
* Add plusarg to enable ECALL insn in main randomized body (Harry
Callahan)
Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>
This commit adds another field in SpikeCosim class so that Spike
can hardcode the correct event registers.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Previously it was sourced from the OpenSUSE build service. This has
produced some reliability issues. Downloading pre-built binaries from a
GCP bucket should improve things.
This addresses a current testbench issue where asserting debug_req_i close to
when single_stepping over an instruction causes an incorrect 'cause' to be
recorded within DCSR.
This builds upon the cosimulation environment to allow us to rip-out all the
existing checking from the test, and instead focus on generating good stimulus
to hit all our coverage points.
Make use of the riscv-dv changes to insert ecall into the main test body, now
that we have a different mechanism for ending the test.
Allow illegal instructions, csr instructions, ebreak, etc. which the previous
brittle checking paradigms could not handle.
This commit adds a new field to the trr (test-run-result) structured data
that records the failure_mode of a testcase. If the test failed due to a
timeout, print a small addendum {T} to each log-line in the summary.
eg.
23.33% PASS 7 PASSED, 23 FAILED
riscv_debug_basic_test.21259: PASS
riscv_debug_basic_test.21260: FAILED {T}
riscv_debug_basic_test.21261: PASS
riscv_debug_basic_test.21262: FAILED {T}
riscv_debug_basic_test.21263: FAILED {T}
riscv_debug_instr_test.21259: FAILED {T}
riscv_debug_instr_test.21260: FAILED {T}
riscv_debug_instr_test.21261: FAILED {T}
riscv_debug_instr_test.21262: PASS
riscv_debug_instr_test.21263: FAILED {T}
riscv_dret_test.21259: FAILED
riscv_dret_test.21260: FAILED
riscv_dret_test.21261: FAILED {T}
Observing the spec change:
RISC-V Debug Support Version 1.0.0-STABLE
1.2.1.4 New Features from 0.13 to 1.0
> 8. Move scontext, renaming original to mscontext, and create hcontext. #535
MSCONTEXT is a backwards-compatible alias to SCONTEXT
In Ibex, SCONTEXT is a read-only zero register. Hence MSCONTEXT has the same behaviour.
Previously it had two packed dimensions. In general we prefer the use of
unpacked arrays for this kind of usage. In particular this had an impact
on trace viewing in GTKWave, the two dimensions were flattened into a
single large bus which made determining individual register values
tricky.
core_ibex_directed_test has a 'disable fork' that was killing processes
that were running sequences. Another part of the testbench waits for
those sequences to finish. When this 'disable fork' happens too early
the sequences are killed before they finish so the testbench never
terminated and times out. Instead ensure the sequences have finished
before doing the 'disable fork'.
The ic_scr_key_valid field indicates whether the ICache scrambling key
is valid.
CPUCTRL is also renamed CPUCTRLSTS as it contains both control and
status bits.
Referring to specific parts of a specific version of the specification
can be brittle as all of these references need to be updated when we
shift specification versions. It's also redundant it should be generally
understood Ibex implements the RISC-V specifications and many lines
could have comments that point to the part of the specification they are
implementing. Rather than having a few of these for no particular reason
easier to just remove them all.
This is specification change between the v1.11 and v1.12 privileged
architectures. Previously mprv wasn't altered on mret. Now if returning
to a privilege level other than M mode mprv must be cleared.
This adds the following CSRs to support the v1.12 priviledged spec.
- MSTATUSH
- MCONFIGPTR
- MENVCFG
- MENVCFGH
MCONFIGPTR is read only and has its value provided by a ibex_pkg
parameter CSR_MCONFIGPTR_VALUE which is set to 0. Implementors can alter
this value if needed.
All the other CSRs ignore writes and read as 0.
RISCV-DV by default sets up some PMP regions. This leads to PMP failures
within riscv_mem_error_test which it isn't expecting. Suppress the PMP
setup to prevent this issue.
Spike has a hack that decrements mcycle/minstret when written.
Previously this was not handled correctly by cosim. As we can only write
32 bits at a time two writes must be used and incremented to counteract
the decrementing handled carefully.
The prior system of using a patch to alter the riscv_dv_setting.sv file
has been removed and replaced with a mako templating based approach.
Fixes#1787
