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Author SHA1 Message Date
Andreas Traber
b0a9e37c63 Fix hwloops, registers were stalled when they should have been active 2015-11-19 11:16:39 +01:00
Andreas Traber
89fec097fb Cleanup branch signals, remove old signals that were no longer used 2015-11-19 10:53:12 +01:00
Andreas Traber
f5d408d7f4 Add an instr_valid_id signal to completely decouple the pipeline stages, 
hopefully fixes the exception controller
 2015-11-18 19:44:05 +01:00
Andreas Traber
4a166db65b rename signals and try to make the whole thing a tiny bit faster 2015-11-18 19:44:05 +01:00
Andreas Traber
8a8b406a6c Finally restyle the debug unit 2015-11-18 17:57:58 +01:00
Andreas Traber
cb73d88ed2 Fix a bug in the PCER CSR registers, it was not possible to activate more than the basic performance counter 2015-11-18 17:22:07 +01:00
Andreas Traber
c7cec664ac Merge remote-tracking branch 'origin/master' into exc_ctrl 2015-11-17 10:36:15 +01:00
Sven Stucki
ec00ad8376 Add lp.setupi instruction 
Hardware loops now have their own adder and no longer share it with the jump
target calculation.

The new lp.setupi instruction makes it possible to truly setup hardware loops
with a single instruction. For the lp.setup instruction, a register with the
counter had to be prepared first. The range of the new instruction is quite
limited though, it uses the shifted z-imm (5 bit, unsigned).
 2015-11-03 17:44:17 +01:00
Sven Stucki
c001c323de Change PULP custom opcodes 2015-11-03 15:38:23 +01:00
Sven Stucki
b99a8b90ba Raise an illegal instruction exception for ecall/scall instructions. 
Those instructions are no yet supported by the (exception) controller and have
been ignored until now. By causing an exception, they can at least be handled
in software if needed in the future.
 2015-11-02 13:35:48 +01:00
Sven Stucki
286b82146c Remove some spaces 2015-10-30 13:50:16 +01:00
Sven Stucki
98eb2cc044 Fix debug breakpoints and single-step with branches in ID 2015-10-29 14:12:50 +01:00
Sven Stucki
a770811ad4 Fix debug breakpoints (dbg_set_npc) 2015-10-29 14:01:53 +01:00
Sven Stucki
0fcdbf130f Add test_en to register file clock gates 2015-10-28 12:47:33 +01:00
Andreas Traber
9532d68a71 Add test_en to core and propagate it to manual clock gates 
Change line endings in register file to unix
 2015-10-28 10:11:16 +01:00
Sven Stucki
82cf8ec258 Fix PPC/NPC tracking of debug unit 2015-10-27 18:31:49 +01:00
Sven Stucki
9efbaeba63 Add register for last branch PC 
Needed in the debug unit, could be reused for precise exceptions.
 2015-10-27 17:50:44 +01:00
Sven Stucki
05b44f97c0 Fix CSR access for debug unit 2015-10-27 17:18:31 +01:00
Sven Stucki
6773f4e3e1 Fix indentation in debug unit 2015-10-27 17:00:12 +01:00
Sven Stucki
d574cac20b Fix problem with debug not working 2015-10-27 16:36:53 +01:00
Sven Stucki
c78a5a6954 Only read CSR when accessed 2015-10-27 14:15:09 +01:00
Sven Stucki
0b0b4c0c29 Fix performance counter access 2015-10-27 12:54:17 +01:00
Sven Stucki
bdb70cd4cc Update compressed decoder to RVC 1.9 2015-10-27 12:39:59 +01:00
Andreas Traber
ad57e4effa Only access CSR registers when we actually care about the rdata 
This silences a warning in simulation and might also help for energy
consumption
 2015-10-27 10:09:59 +01:00
Sven Stucki
b1862dd33a Merge branch 'master' into exc_ctrl 2015-10-25 19:33:02 +01:00
Sven Stucki
f8dbb7ed92 Fix bug with hardware loops 2015-10-25 19:26:46 +01:00
Sven Stucki
9ee009a219 Fix exc controller ack not being sent 2015-10-23 16:49:16 +02:00
Sven Stucki
d2c8159a2d Fix bug in csrrc instruction 2015-10-23 12:15:33 +02:00
Sven Stucki
3f6ba69413 Add first version of bad memory access exceptions 2015-10-22 13:20:43 +02:00
Sven Stucki
9f5beb527f Fix comparison bug in ALU 2015-10-21 17:45:32 +02:00
Sven Stucki
459e34f747 Add error signals to LSU 2015-10-19 19:43:58 +02:00
Sven Stucki
906b51305e Fix irq_enable 2015-10-19 19:42:10 +02:00
Sven Stucki
30318e694a Fix interrupt not executed early enough after sleep 2015-10-19 19:42:10 +02:00
Sven Stucki
8d4c069d84 Fix exceptions during stalls 2015-10-19 19:42:10 +02:00
Sven Stucki
c28ca4444a Fix exc wiring (not working yet) 2015-10-19 19:42:10 +02:00
Sven Stucki
c68a098059 Initial commit of updated exception controller 
Largely untested, but should be wired up correctly.
 2015-10-19 19:40:37 +02:00
Sven Stucki
b957c6f682 Merge branch 'remove_vect' 
This commit removes the vectorial ALU and updates RVC to the newest proposal.
 2015-10-18 19:57:42 +02:00
Sven Stucki
26394abcaf Fix/Update compressed decoder for newest RVC 1.8 draft 2015-10-18 19:28:41 +02:00
Andreas Traber
97a3ded4e3 Fix typo in last commit 2015-10-16 14:34:33 +02:00
Andreas Traber
7936609c2a Fix a bug in the load store unit which allowed to send requests when the 
last one was waiting for rvalid. This may increase critical path
slightly, but otherwise it is simply not correct...

Added assertions to catch those cases
 2015-10-16 14:33:18 +02:00
Sven Stucki
7d06e4ab62 Fix c.addi16sp and RVC B immediates 2015-10-14 15:26:29 +02:00
Sven Stucki
bb09eeeb25 Fix c.j & c.jal immediate encoding 2015-10-14 14:40:56 +02:00
Sven Stucki
f20735d87f Update RVC opcodes 2015-10-14 14:24:02 +02:00
Sven Stucki
189ccf7cd1 Compressed decoder updated to RVC 1.8 before encoding tweak 2015-10-14 10:23:14 +02:00
Andreas Traber
4d2280bc3c Check for invalid branch decision when performing a branch as an 
assertion
 2015-10-12 13:26:55 +02:00
Sven Stucki
770013679e Cleanup tracer and defines 2015-10-08 10:47:04 +02:00
Sven Stucki
c35482dee4 Remove duplicate tracer functions 2015-10-08 10:36:06 +02:00
Sven Stucki
83bccc197e Remove incomplete/no longer used function 2015-10-08 10:10:59 +02:00
Sven Stucki
7223cb5e41 Fix wrongly used unique case 2015-10-08 09:53:28 +02:00
Sven Stucki
563e205cc5 Add hwloop instructions to tracer 2015-10-07 00:34:27 +02:00