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Author SHA1 Message Date
Sven Stucki
c28ca4444a Fix exc wiring (not working yet) 2015-10-19 19:42:10 +02:00
Sven Stucki
c68a098059 Initial commit of updated exception controller 
Largely untested, but should be wired up correctly.
 2015-10-19 19:40:37 +02:00
Sven Stucki
b957c6f682 Merge branch 'remove_vect' 
This commit removes the vectorial ALU and updates RVC to the newest proposal.
 2015-10-18 19:57:42 +02:00
Sven Stucki
26394abcaf Fix/Update compressed decoder for newest RVC 1.8 draft 2015-10-18 19:28:41 +02:00
Andreas Traber
97a3ded4e3 Fix typo in last commit 2015-10-16 14:34:33 +02:00
Andreas Traber
7936609c2a Fix a bug in the load store unit which allowed to send requests when the 
last one was waiting for rvalid. This may increase critical path
slightly, but otherwise it is simply not correct...

Added assertions to catch those cases
 2015-10-16 14:33:18 +02:00
Sven Stucki
7d06e4ab62 Fix c.addi16sp and RVC B immediates 2015-10-14 15:26:29 +02:00
Sven Stucki
bb09eeeb25 Fix c.j & c.jal immediate encoding 2015-10-14 14:40:56 +02:00
Sven Stucki
f20735d87f Update RVC opcodes 2015-10-14 14:24:02 +02:00
Sven Stucki
189ccf7cd1 Compressed decoder updated to RVC 1.8 before encoding tweak 2015-10-14 10:23:14 +02:00
Andreas Traber
4d2280bc3c Check for invalid branch decision when performing a branch as an 
assertion
 2015-10-12 13:26:55 +02:00
Sven Stucki
770013679e Cleanup tracer and defines 2015-10-08 10:47:04 +02:00
Sven Stucki
c35482dee4 Remove duplicate tracer functions 2015-10-08 10:36:06 +02:00
Sven Stucki
83bccc197e Remove incomplete/no longer used function 2015-10-08 10:10:59 +02:00
Sven Stucki
7223cb5e41 Fix wrongly used unique case 2015-10-08 09:53:28 +02:00
Sven Stucki
563e205cc5 Add hwloop instructions to tracer 2015-10-07 00:34:27 +02:00
Andreas Traber
06cf9f1dfe Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
Sven Stucki
c17e0d298f Optimize stores: write data is passed through operand c, remove unneeded 32 bit register 2015-10-02 15:03:49 +02:00
Sven Stucki
35f88d7221 Fix indentation in riscv_core 2015-10-02 14:24:38 +02:00
Sven Stucki
2911b8df2f Cleanup ALU/mult ports 2015-10-02 14:07:44 +02:00
Sven Stucki
411e074f7e Cleanup ALU, remove all vector operations 2015-10-02 13:56:44 +02:00
Sven Stucki
4a83cf3d9e Cleanup EX stage a bit 2015-10-02 11:03:20 +02:00
Sven Stucki
5cafb9b463 Cleanup hwloop section a bit 2015-10-02 10:51:12 +02:00
Sven Stucki
3f13d89764 Bypass mux for rs3 as ALU op B 2015-10-02 10:47:39 +02:00
Sven Stucki
a4bba8950e Rename rs3 signals in ID 
TODO: Check for potential side effects
 2015-09-30 18:52:19 +02:00
Sven Stucki
443762ab6b Remove vector control signals from decode -> Ex 2015-09-30 18:43:00 +02:00
Sven Stucki
1211237494 Remove vectorial stuff from multiplier 2015-09-30 18:40:56 +02:00
Sven Stucki
88fb2adac3 Add many ALU instructions from OR10N 2015-09-30 18:23:42 +02:00
Sven Stucki
715265d61d Add MAC with subword selection 2015-09-30 16:50:03 +02:00
Sven Stucki
076930ad64 Correctly deassert mac_en_o too 2015-09-30 16:31:52 +02:00
Sven Stucki
66e2c9b48b Edit comments in decoder 2015-09-30 16:31:52 +02:00
Andreas Traber
e001a6e745 Not taken branches do no longer waste cycles 2015-09-30 13:06:22 +02:00
Sven Stucki
fbd897a233 Fix forwarding of rs3 2015-09-29 17:45:21 +02:00
Sven Stucki
8fa5f6a522 Add reg-reg and post-increment load/stores to tracer 2015-09-29 14:10:29 +02:00
Sven Stucki
9ff25b5a1d Add MAC instruction, update regc (i.e. rs3) position 2015-09-25 14:14:01 +02:00
Sven Stucki
3a992372d6 Merge branch 'rvc18' 
Adds support for the updated RVC extension. The spec is not final yet, but the
compiler already supports and uses it. This update makes it possible to use
the most up-to-date compiler version.
 2015-09-25 13:19:41 +02:00
Andreas Traber
1aa8b78a73 Prefetcher now tells the core when it is safe to shut down 2015-09-24 16:32:17 +02:00
Andreas Traber
4571bc30ae Make instr_addr_o in prefetcher independent of instr_rvalid_i 2015-09-24 13:20:11 +02:00
Andreas Traber
efb607a792 Fix exception problem after stages are more independent 2015-09-24 13:16:18 +02:00
Andreas Traber
415546609e Simplify rdata output from prefetcher, we can simply use the higher part 
of rdata_o for rdata_unaligned_o, it's the same after all, always
 2015-09-24 09:59:04 +02:00
Andreas Traber
2f89182e8b Clear prefetch bit when branch is incoming 2015-09-24 09:32:28 +02:00
Andreas Traber
cc90e85471 Fix RVC handling in prefetch_L0_buffer 
The code is not so nice and should be further cleaned up
 2015-09-23 17:25:15 +02:00
Andreas Traber
b41b2a697d Further cleanups, try to make the code a bit easier to understand... 2015-09-23 17:25:15 +02:00
Flo Zaruba
d988f06f0e Fixed synopsis syntax error 2015-09-23 15:44:03 +02:00
Andreas Traber
88614ea124 Fix id_valid signal propagation to exception controller 2015-09-23 15:33:02 +02:00
Andreas Traber
a3256c4df2 Fix small error in prefetcher where GNT occur one cycle after we wanted 
to prefetch
 2015-09-23 15:32:30 +02:00
Sven Stucki
b5c885b027 Cleanup compressed decoder 2015-09-23 14:12:34 +02:00
Sven Stucki
6ececfc676 Update compressed_decoder to RVC v1.8 2015-09-23 14:11:42 +02:00
Andreas Traber
9ceeb15bc8 This fixes the instruction fetch miss performance counter 2015-09-22 16:35:16 +02:00
Andreas Traber
072cd65e65 Change indentation of prefetch buffer to match RI5CYs style 2015-09-22 12:50:28 +02:00