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Author	SHA1	Message	Date
felsabbagh3	1b25b10644	Full Evaluation Attempt 1	2019-09-11 01:39:00 -04:00
felsabbagh3	3c3a443bd5	New RF with Evaluation	2019-09-11 01:04:23 -04:00
felsabbagh3	8d143d7739	Quartus + GPR evaluation	2019-09-10 20:23:01 -04:00
felsabbagh3	4e8da1811a	New GPR structure - Clone or WSPAWN	2019-09-09 22:17:20 -04:00
felsabbagh3	1882147370	GPR Wrapper Interface Done	2019-09-09 14:04:07 -04:00
felsabbagh3	bce9bc443c	GPR Wrapper in Decode	2019-09-09 01:03:13 -04:00
felsabbagh3	ecf81336db	Finished FE and BE high-level	2019-09-08 19:28:53 -04:00
felsabbagh3	981bf0afe5	FE Done	2019-09-08 18:36:47 -04:00
felsabbagh3	ad45758a35	Before Fetch->FE	2019-09-08 18:09:11 -04:00
felsabbagh3	c310e7381f	Icache interface	2019-09-08 17:36:09 -04:00
felsabbagh3	5e6804703f	Decode in FE	2019-09-08 17:24:51 -04:00
felsabbagh3	ac9b06bf7d	Before FE BE abstraction	2019-09-08 16:21:37 -04:00
felsabbagh3	fe09aafbb4	Interface Checkpoint 2 - Remove Lints	2019-09-05 19:32:37 -04:00
felsabbagh3	2d0e41db63	checkpoint: Added icache struct	2019-09-03 16:19:06 -04:00
felsabbagh3	cde45648ea	Added Bug coments	2019-06-12 08:27:48 -07:00
felsabbagh3	3e93301846	Added Bug coments	2019-06-12 08:26:04 -07:00
felsabbagh3	32d1bfb140	Barrier bug comment	2019-06-12 08:22:03 -07:00
felsabbagh3	db0860a7fb	Recompiled kernel	2019-06-12 08:09:31 -07:00
felsabbagh3	b76d819d82	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2019-06-12 08:03:59 -07:00
felsabbagh3	b3256a7b7f	Fix barrier bug	2019-06-12 08:03:30 -07:00
Hyesoon Kim	6b3b124a30	fix typo of std=c++11	2019-06-12 07:32:20 -04:00
felsabbagh3	9cd8ee8579	Added std=c++11	2019-06-11 23:21:48 -07:00
felsabbagh3	1105261bbb	Updated Quartus paths	2019-06-11 21:16:50 -07:00
felsabbagh3	b216da5a6a	ram stdint + Quartus Files	2019-06-11 21:13:30 -07:00
felsabbagh3	d7afef04a9	Sim Work miss	2019-05-18 23:42:55 +04:00
felsabbagh3	8995267cd3	Added barriers	2019-05-17 08:34:00 +04:00
felsabbagh3	48468ed26a	Proper SIMT with fine-grain scheduler implemented	2019-05-10 00:49:54 -07:00
felsabbagh3	96dac5e1ce	Warp + Context Aware Design - Global Stalling	2019-05-08 16:32:49 -07:00
felsabbagh3	a6c13bc38c	Inefficient context aware desgin	2019-05-08 15:55:06 -07:00
felsabbagh3	79356c7ab1	Changed hierarchy + Identified private + public modules	2019-05-07 23:45:05 -07:00
felsabbagh3	191ed73415	Less expensive but slower fetch logic	2019-05-05 22:55:47 -04:00
felsabbagh3	f21eaec79f	Provisioned SM	2019-04-05 19:25:54 -04:00
felsabbagh3	166b9ae48d	Before Scratchpad	2019-04-05 17:56:05 -04:00
felsabbagh3	719ed25213	Cleanup	2019-03-31 16:30:37 -04:00
felsabbagh3	26378d61d8	updated TODO	2019-03-31 05:22:42 -04:00
felsabbagh3	8c2ae97510	1 WARP 8 THREADS TESTED + FULLY WORKING	2019-03-31 05:21:00 -04:00
felsabbagh3	c83ef94d02	1 WARP 2 THREADS WORKING	2019-03-31 05:02:55 -04:00
felsabbagh3	4aac33b298	Using verilog For-loops + Passing all tests	2019-03-30 22:55:13 -04:00
felsabbagh3	52a839f84d	Using verilog For-loops + Passing all tests	2019-03-30 22:14:44 -04:00
felsabbagh3	a3a3b21de7	Using verilog For-loops + Passing all tests	2019-03-30 22:09:03 -04:00
felsabbagh3	99a0792a0c	Passing all tests with 2 threads	2019-03-30 03:54:20 -04:00
felsabbagh3	d02c3d25b7	sync	2019-03-27 13:52:13 -04:00
felsabbagh3	68f3ba84e5	Added HW threads - Infinite loop + fixed valid	2019-03-27 03:53:59 -04:00
felsabbagh3	9b42e79dcf	Added HW threads - Infinite loop	2019-03-27 03:44:14 -04:00
felsabbagh3	cc0fb0eece	better use of valid signal	2019-03-27 00:07:59 -04:00
felsabbagh3	7a528c5ef2	Packing data wires + ALU module	2019-03-26 19:17:11 -04:00
felsabbagh3	6901208a54	Added a README	2019-03-22 04:29:24 -04:00
felsabbagh3	d42e7845a9	Added a README	2019-03-22 04:27:42 -04:00
felsabbagh3	781c11c93f	Updated TODO	2019-03-22 04:21:21 -04:00
felsabbagh3	6c64fa35f8	Restructure	2019-03-22 04:14:52 -04:00