78 commits

Author	SHA1	Message	Date
tinebp	001a107395	bram reset bug fix	2025-01-20 22:16:05 -08:00
tinebp	83ba1cc3dc	minor update	2025-01-11 20:23:26 -08:00
tinebp	a98d2e24e5	rtlsim multibanks	2024-12-16 22:10:57 -08:00
tinebp	18bf49d1e0	minor update	2024-11-21 16:48:18 -08:00
tinebp	320c090613	xilinx asynchronous bram patch fixes	2024-11-19 01:57:33 -08:00
tinebp	bffc6d9610	enabling Vivado's asynchronous bram suppot via direct netlist transformation	2024-11-13 16:20:25 -08:00
Blaise Tine	6f81df5edb	axi_adapter large tags support	2024-09-30 06:25:50 -07:00
Blaise Tine	6e40162027	extending scope triggering to capture continous firing events	2024-09-27 11:36:31 -07:00
Blaise Tine	5db1937a5e	fixed scope parser array indexing	2024-09-27 07:52:38 -07:00
Blaise Tine	9a3eb74051	adding scope.py support for structs	2024-09-26 09:50:38 -07:00
Blaise Tine	50458bbae0	xilinx synthesis debugging foxes	2024-09-17 06:22:07 -07:00
Blaise Tine	e4bfa47895	adding test coverage for xilinx synthesis	2024-08-22 02:51:17 -07:00
Blaise Tine	1814ff6d40	xilinx standalone synthesis fixes	2024-08-18 22:02:37 -07:00
Blaise Tine	62a4ee7a3e	minor update	2024-08-17 05:32:21 -07:00
Blaise Tine	8fe02093e2	minor udpate	2024-08-17 04:11:16 -07:00
Blaise Tine	69fdb4bd04	mino rupdate	2024-04-15 19:23:20 -07:00
Blaise Tine	03cf694238	minor update	2024-03-30 05:33:57 -07:00
Blaise Tine	9e54ccde6d	adding support for top-module parameter replacement during synthesis tests	2024-02-10 21:54:35 -08:00
Blaise Tine	c1e168fdbe	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update	2023-11-10 02:47:05 -08:00
Blaise Tine	d7737542e4	cache uuid support	2021-12-09 20:43:22 -05:00
Blaise Tine	41d7e6c63a	cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes	2021-11-30 07:08:15 -05:00
Blaise Tine	fe862f64b1	dispatch refactoring	2021-10-19 15:16:00 -04:00
Blaise Tine	e380ded5e1	Merge branch 'master' into graphics	2021-10-15 19:32:11 -07:00
Blaise Tine	1cd833d2c4	minor fixes	2021-10-11 19:02:13 -07:00
Blaise Tine	29aba92bf1	minor update	2021-09-30 06:14:05 -07:00
Blaise Tine	a801a16062	instruction decode refactoring fixing naming collision	2021-08-29 20:07:34 -07:00
Blaise Tine	4336dcb2a8	minor scope analyzer fix	2021-08-13 19:23:57 -07:00
Blaise Tine	cc259f60f6	minor update	2021-08-11 15:39:21 -07:00
Blaise Tine	4e4aa33a50	minor update	2021-08-08 03:09:28 -07:00
Blaise Tine	0debdd3fe7	minor update	2021-08-08 02:59:30 -07:00
Blaise Tine	b1eef0fb7c	warp scheduler optimization	2021-08-07 23:45:01 -07:00
Blaise Tine	7b921387bc	Merge branch 'master' into graphics	2021-08-02 23:57:53 -07:00
Blaise Tine	3b7da61245	minor update	2021-07-31 03:30:35 -07:00
Blaise Tine	ee46bc8a48	minor update	2021-07-31 03:02:25 -07:00
Blaise Tine	94ad34768b	Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics ... Conflicts: hw/rtl/VX_core.v hw/rtl/VX_csr_data.v hw/rtl/VX_csr_unit.v hw/rtl/VX_decode.v hw/rtl/VX_define.vh hw/rtl/VX_execute.v hw/rtl/VX_gpu_unit.v hw/rtl/VX_instr_demux.v hw/rtl/VX_lsu_unit.v hw/rtl/VX_mem_unit.v hw/rtl/VX_pipeline.v hw/rtl/VX_platform.vh hw/rtl/VX_smem_arb.v hw/rtl/VX_writeback.v hw/rtl/cache/VX_bank.v hw/rtl/interfaces/VX_cache_mem_req_if.v hw/rtl/interfaces/VX_cache_mem_rsp_if.v hw/rtl/interfaces/VX_dcache_core_rsp_if.v hw/rtl/interfaces/VX_dcache_req_if.v hw/rtl/interfaces/VX_icache_core_rsp_if.v hw/rtl/tex_unit/VX_tex_memory.v hw/rtl/tex_unit/VX_tex_unit.v hw/simulate/Makefile hw/syn/quartus/pipeline/Makefile hw/unit_tests/tex_unit/tex_sampler/main.cpp hw/unit_tests/tex_unit/tex_sampler/vl_simulator.h runtime/include/vx_intrinsics.h	2021-07-30 21:12:55 -07:00
Blaise Tine	4ffbcb336f	minor update	2021-07-22 14:20:02 -07:00
Blaise Tine	7e0dc81cee	minor update	2021-06-23 04:19:13 -07:00
Blaise Tine	41069ba188	non-cacheable memory address fixes	2021-06-06 20:54:36 -07:00
Blaise Tine	3071fb7a29	adding support for non-cacheable memory addressing	2021-06-06 13:35:55 -07:00
Blaise Tine	30a39afbf6	master merge fixes	2021-05-27 16:50:03 -07:00
Blaise Tine	762c5da237	minor update	2021-05-27 15:23:58 -07:00
Blaise Tine	d42171d2ed	Merge branch 'master' into graphics	2021-05-26 23:33:06 -07:00
Blaise Tine	8f451aa74c	minor update	2021-05-04 08:01:49 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	4cb98a25a7	enabling 128-bit dram bus	2021-04-24 00:31:27 -04:00
Blaise Tine	676a13f30d	tex refactoring and bug fixes	2021-03-16 09:25:57 -04:00
Blaise Tine	b023496ecb	minor update	2021-03-01 03:00:58 -08:00
Blaise Tine	7560202f8b	cache bank refactoring - removing unecessary core response fifo & restoring single port data access	2021-02-21 21:47:46 -08:00
Blaise Tine	a046bd7a73	cache pipeline optimization	2021-01-17 17:19:52 -08:00
Blaise Tine	d4e7b28be8	cache refactoring	2021-01-17 00:18:56 -08:00