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3373 commits 27 branches 9 tags 1.6 GiB
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143 commits

Author SHA1 Message Date
tinebp
704f525fd6 memory mem_coalescer miss perf counter 
RTL perf counters refactoring
 2024-12-26 08:00:36 -08:00
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6d5e71a062 minor update 2024-08-25 20:12:05 -07:00
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f6ed49f19c minor update 2024-08-16 08:19:55 -07:00
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2b22d47dd9 minor update 2024-08-15 05:11:19 -07:00
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bddf276335 memory request flags refactoring 2024-08-06 19:05:22 -07:00
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4b73762aea profiling optimizations 2024-07-19 00:18:53 -07:00
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3efced37c5 trace INSTANCE_ID refactoring 2024-07-09 13:33:17 -07:00
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1322499c3f minor update 2024-07-09 13:05:43 -07:00
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f0a4d2e142 minor update 2024-07-09 11:48:29 -07:00
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a72c68acf4 minor update 2024-05-23 22:33:12 -07:00
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b3f96e288a + support for ZICOND RISC-V extension 
+ RTL decode refactoring
 2024-05-20 00:17:24 -07:00
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ca79e69355 SIMT Tack compression 2024-04-30 02:19:32 -07:00
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135cc4f5a7 minor update 2024-04-09 01:58:04 -07:00
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03cf694238 minor update 2024-03-30 05:33:57 -07:00
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ae12b45f77 minor update 2024-03-25 15:01:40 -07:00
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c175e11a18 Using packed LSU memory requests within the code 2024-03-18 21:22:02 -07:00
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bb4c150aaf per-warp ibuffer scoreboard scheduling optimization 2024-02-14 14:24:47 -08:00
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8ab7c590fd disabling fetch's deadlock check when L1 caches are present 2024-01-31 06:16:54 -08:00
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e217bc2c23 adding tracking for SFU stalls 2023-12-28 12:12:11 -08:00
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c7a81d1493 adding sockets support to simx and cache subsystem refactoring 
minor update

minor update

minor updates
 2023-12-20 15:16:12 -08:00
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e04e026a14 profiling update 
minor updates
 2023-12-18 04:43:44 -08:00
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24973ffca0 scoreboard optimization & profiling 2023-11-27 05:53:36 -08:00
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d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
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d7737542e4 cache uuid support 2021-12-09 20:43:22 -05:00
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41d7e6c63a cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes 2021-11-30 07:08:15 -05:00
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fe862f64b1 dispatch refactoring 2021-10-19 15:16:00 -04:00
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e248f744d5 Merge branch 'master' of https://github.com/vortexgpgpu/vortex 2021-10-19 03:07:13 -04:00
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58a2140b92 merge update 2021-10-15 19:58:13 -07:00
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e380ded5e1 Merge branch 'master' into graphics 2021-10-15 19:32:11 -07:00
Santosh Raghav Srivatsan
dd12d3f848 vortex tutorial assignment 5 solution 2021-10-15 18:25:54 -04:00
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04249c3ee9 code refactoring for Vivado compatibility 2021-09-29 04:48:53 -04:00
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a45261b530 code refactoring for Vivado compatibility 2021-09-29 03:24:17 -04:00
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18c1dc2f0e fixed interface modports 2021-09-28 02:42:04 -07:00
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9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility 2021-09-27 08:55:10 -04:00
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3d052e9428 fmax optimization bundle (250 MHz). 2021-09-08 02:26:39 -07:00
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05bc970900 minor update 2021-09-07 23:57:14 -07:00
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3e014c8285 fmax optimizations bundles 2021-09-06 01:36:57 -07:00
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b52ace5142 area optimization bundle 2021-09-05 23:35:44 -07:00
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a801a16062 instruction decode refactoring fixing naming collision 2021-08-29 20:07:34 -07:00
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b1eef0fb7c warp scheduler optimization 2021-08-07 23:45:01 -07:00
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b5af2065ee fetch optimization 2021-08-07 12:57:14 -07:00
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e4d9fd8a00 thread mask redesign 2021-08-05 17:32:58 -07:00
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7b8fe11e6a unused variables refactoring 2021-08-05 01:46:26 -07:00
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bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
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0319283ea7 minor update 2021-07-20 21:42:22 -07:00
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8048796102 minor update 2021-07-20 21:23:31 -07:00
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aa7b0da877 minor update 2021-07-20 21:07:41 -07:00
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d3b788784a memory interface refactoring 2021-07-20 21:06:55 -07:00
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382585d33d minor update 2021-07-17 07:22:16 -07:00
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5c40422e4f dcache response bus optimization 2021-07-12 10:14:48 -07:00