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Author	SHA1	Message	Date
CoralieAllioux	367fe5850a	[Xcelium flow] corev dv yaml (#2210)	2024-06-12 09:44:44 +02:00
Akiho Kawada	bc7149adc7	refactor hpdcache_cache_subsystem module code to ease reutilization (#2173)	2024-06-11 23:12:30 +02:00
slgth	f57a6c0106	Move CV32A65X documentation into its own chapter (#2236)	2024-06-11 18:01:25 +02:00
JeanRochCoulon	4391fc4b14	Use cv32a6_imac_sv32 to generate FPGA bitstream (#2229)	2024-06-11 16:25:07 +02:00
André Sintzoff	546a8c26da	csr_regfile.sv: if no U-mode, mstatus.tw is read-only 0 (fix #2228) (#2233)	2024-06-11 15:08:28 +02:00
JeanRochCoulon	91871d97f3	Update functionality.rst (#2235)	2024-06-11 12:31:52 +02:00
JeanRochCoulon	2266f75f2d	MTVAL is read-only zero when TvalEn = 0 (#2231)	2024-06-11 11:22:41 +02:00
JeanRochCoulon	9d02734bd1	Fix PMPCFG number (from 8 to 4, from which 2 are read-only zero) (#2232)	2024-06-11 11:15:27 +02:00
André Sintzoff	afb3265296	csr_regfile.sv: if no U-mode, mcounteren does not exist (fix #2221) (#2227)	2024-06-10 21:42:00 +02:00
JeanRochCoulon	7ccf82ce76	Add param to enable/disable Zihpm and Zicntr extensions for 65x (#2208)	2024-06-10 15:14:03 +02:00
JeanRochCoulon	dc000d6c37	Define a new param to constraint mtvec to be in direct mode only (#2226)	2024-06-10 11:59:54 +00:00
Jalali	feb35f2b88	Fix Csr instruction decode and change the message verbosity (#2225)	2024-06-10 13:22:05 +02:00
Côme	eac60af1a9	superscalar: add a second issue port (#2209)	2024-06-09 20:47:09 +02:00
dependabot[bot]	424eca6f63	Bump verif/core-v-verif from b92d30f to 835720b (#2215)	2024-06-09 20:40:00 +02:00
Mathieu Gouttenoire	ade4c85e13	Remove extra -v in smoke-tests.sh (#2207)	2024-06-06 16:51:17 +02:00
Zbigniew Chamski	592487ffa0	[riscv-config] Align CV32A65X spec on adoc, cleanup defs. Fix CSR updater. (#2206)	2024-06-06 11:19:41 +02:00
Jalali	278649d3ed	Update coverage script after exclude HPDcache module (#2197)	2024-06-05 09:55:48 +02:00
Jalali	35255e1c47	Exclude HPD cache module from code coverage (#2194)	2024-06-04 23:30:36 +02:00
Zbigniew Chamski	aa76752f18	Update riscv-config infra to better match expressivity needs of CV32A65X. (#2193)	2024-06-04 18:12:14 +02:00
MarioOpenHWGroup	721fa0c175	Fix Github CI by changing riscv-isa-sim hash (#2190)	2024-06-04 12:33:21 +02:00
Guillaume Chauvon	a5152b03a5	Add support for cv32a65x dedicated synthesis (#2178)	2024-06-04 10:58:09 +02:00
AbdessamiiOukalrazqou	e0da6e3569	Fix access issues for reserved fields (#2187)	2024-06-03 15:54:10 +02:00
AEzzejjari	1c828c0a16	Connect the new AXI agent with CVA6 (#2182)	2024-06-03 14:42:37 +02:00
André Sintzoff	ba6262a65c	add Unprivileged RISC-V ISA for CV32A65X doc (#2186)	2024-06-03 12:13:16 +02:00
Jalali	8e2393db99	Add the capability to add functional coverage results into the dashboard (#2183)	2024-06-03 11:47:22 +02:00
MarioOpenHWGroup	d89c5b6ba6	Disable misa we in rm (#2181)	2024-06-03 10:58:22 +02:00
AngelaGonzalezMarino	3e907d625f	fix tval in mmu (#2124)	2024-05-31 15:26:33 +02:00
André Sintzoff	227a3f4ff9	doc cv32a65x: update xPELP fields in mstatus (#2177)	2024-05-31 12:48:12 +02:00
Jalali	ae4392e958	CORE-DV : Merge all exception handlers in one to optimize time simulation (#2175)	2024-05-31 12:39:58 +02:00
Jalali	9ddebe25ae	HOTFIX : ignore instr_addr_misaliged exception only when also there's a trap (#2174)	2024-05-31 12:39:48 +02:00
Zbigniew Chamski	c30c20bc2b	[riscv-config] HOTFIX: Regenerate output files for CV32A65X. (#2176)	2024-05-31 12:39:10 +02:00
Cyprien Heusse	46e9d5a7fc	32 bits WB cache (#2170)	2024-05-30 18:47:39 +02:00
André Sintzoff	718c4e23b3	update riscv-isa-manual to riscv-isa-release-1bec7d3-2024-05-28 (#2169)	2024-05-30 17:54:30 +02:00
MarioOpenHWGroup	d714d833cb	Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044)	2024-05-30 15:57:58 +02:00
JeanRochCoulon	0da83492f6	Give information on how to clean-up Spike before build (#2164)	2024-05-30 13:40:51 +02:00
JeanRochCoulon	8630458370	Parametrization: Use CVA6Cfg.WtDcacheWbufDepth in place of DCACHE_WBUF_DEPTH (#2166)	2024-05-30 12:26:58 +02:00
Côme	93648e8cf7	Revert "Functional coverage report in CI (#2127)" (#2168) ... This reverts commit d4f984dbce.	2024-05-30 10:37:56 +02:00
Jalali	c50c4770f5	TRAPS VERIF : Add checking pc after a trap and remove unnecessary coverage (#2167)	2024-05-30 09:02:24 +02:00
Zbigniew Chamski	2534713373	[riscv-config] Fix issues in CV32A65X input spec and regenerate output. (#2165)	2024-05-29 17:35:47 +02:00
André Sintzoff	4df326e13c	utils.py: format and fix typos (#2163)	2024-05-29 09:37:46 +02:00
JeanRochCoulon	b6495684ba	Insert CSR generated from riscv-config (#2162)	2024-05-29 09:37:31 +02:00
AngelaGonzalezMarino	f8914b9237	Mmu user manual (#2118)	2024-05-28 17:45:22 +02:00
JeanRochCoulon	83191f4c3f	Change spike.yaml location (#2160)	2024-05-28 13:25:43 +02:00
xiaoweish	8cb7a8a4ed	fix gcc-14 compile error on: implicit-function-declaration, implicit-int (#2159)	2024-05-28 07:04:10 +02:00
dependabot[bot]	691c480aea	Bump core/cache_subsystem/hpdcache from 57c82d3 to 32407cb (#2157)	2024-05-27 23:06:50 +02:00
dependabot[bot]	987cbc06c3	Bump verif/core-v-verif from 4e6e860 to 399438e (#2158)	2024-05-27 23:06:20 +02:00
JeanRochCoulon	f0adb7680b	Update the specification following the last commits (RVF, SUPERSCALAR,...) (#2155)	2024-05-27 18:02:40 +02:00
AbdessamiiOukalrazqou	8fbfe3e57a	add gen from riscv config software (#2156)	2024-05-27 18:01:56 +02:00
Zbigniew Chamski	d1c6aab1f0	[UVM TB] Initialize information about DRAM address and size. (#2153)	2024-05-27 16:13:12 +02:00
AEzzejjari	f0deb6104c	axi Specification: Modify the AXI memory interface specification (#1960)	2024-05-27 11:52:27 +02:00