xiaoweish
398778a1ba
Add vcs -full64 option back ( #2294 )
2024-06-26 22:58:55 +02:00
xiaoweish
c93587b1f9
Update UART submodule to version 0.2.1 and Use SV UART in vcs-testharness ( #2196 )
2024-06-17 09:24:18 +02:00
CoralieAllioux
3ed5e78c91
[Xcelium flow] xrun testharness rules ( #2223 )
2024-06-14 14:31:56 +02:00
Guillaume Chauvon
a5152b03a5
Add support for cv32a65x dedicated synthesis ( #2178 )
2024-06-04 10:58:09 +02:00
MarioOpenHWGroup
d714d833cb
Bump verif/core-v-verif from f7bda8e to NOTMERGED ( #2044 )
2024-05-30 15:57:58 +02:00
Cesar Fuguet
cd241cb387
hpdcache: update HPDcache to support parametrization ( #2059 )
2024-05-15 12:28:36 +02:00
Guillaume Chauvon
1c3370950f
Add support for waveform in vcs-testharness ( #2079 )
2024-04-26 14:33:16 +02:00
Florian Zaruba
38e8c059b2
Parameterization and other fixes for downstream project ( #1950 )
...
* Bender fixes and switch to `cva6_fifo_v3`
* cfg: Fix verilator warnings
* Bender: Fix yml
* acc_dispatcher: Add `csr_addr_i`
* parameterization: Fox AXI_USER_EN warning
* wb_cache: Fix Verilator Lint warnings
* cva6_fifo_v3: Add to Flist
* parameterization: Address review concerns
* Switch to `cva6_fifo_v3`
* tracer: Remove tracer interface
The interface made a bunch of problems with the
typedefs so I've removed it.
---------
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2024-04-05 13:02:18 +02:00
Saute0212
5920e3d125
Add support for Nexys Video board ( #1925 )
2024-04-04 11:13:32 +02:00
MarioOpenHWGroup
62bdf11594
Bump core-v-verif d94f0de and fix questa simulator ( #1915 )
2024-03-21 19:02:41 +01:00
Côme
83d94bbb69
transform rvfi types into macros ( #1921 )
2024-03-12 17:34:27 +01:00
MarioOpenHWGroup
c7f0eaf0d8
Bump verif/core-v-verif from fd68dfd to c7d2077 ( #1828 )
2024-02-13 14:20:21 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
MarioOpenHWGroup
e5a0993ef9
Verilator Tandem Support ( #1702 )
2023-12-12 18:49:49 +01:00
valentinThomazic
b6bd2a9583
Clean-up: removed wrong and now useless variable declaration in Makefile ( #1686 )
2023-12-08 15:59:55 +01:00
MarioOpenHWGroup
220f534b6d
Spike Tandem Implementation using VCS simulator ( #1561 )
2023-11-09 19:29:24 +01:00
Saad Waheed
584198427b
[CI] Update Verilator version to v5.008 ( #1566 )
...
Signed-off-by: Saad Waheed <saad.waheed@10xengineers.ai>
2023-10-23 22:38:17 +02:00
Cesar Fuguet
7de1345291
Add the HPDcache as cache subsystem ( #1513 )
...
Add the HPDcache as another alternative for the cache subsystem.
The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.
2023-10-16 09:26:20 +02:00
Zbigniew Chamski
1683c818c4
Streamline installation process (Spike and toolchain variables, README file). ( #1468 )
2023-09-26 16:51:03 +02:00
Côme
5b37393a2e
fix verilator wavedump ( #1395 )
2023-09-13 22:36:19 +02:00
Pascal Cotret
9d6e434ee9
Fix VCD generation from Verilator model ( #1341 )
2023-08-24 06:08:16 +02:00
Zbigniew Chamski
dd65886ac0
[Verilator] Fix trace generation after upgrading VL build process. ( #1327 )
...
* Makefile (verilate_command): Use correct paths to VL trace support files.
2023-08-01 08:54:09 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory ( #1318 )
...
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2023-07-28 08:32:48 +02:00
JeanRochCoulon
716d21c424
Define AXI as cva6 input parameters ( #1315 )
...
* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
2023-07-24 10:34:30 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
JeanRochCoulon
42cfa58ddc
Revert "Makefile: Remove duplicate cva6_config_pkg ( #1273 )" ( #1286 )
...
This reverts commit ae97ddb660
2023-06-28 23:02:30 +02:00
Nils Wistoff
ae97ddb660
Makefile: Remove duplicate cva6_config_pkg ( #1273 )
2023-06-23 08:38:52 +02:00
Nils Wistoff
f56286de31
Makefile/questa: Pass elf-bin to fesvr ( #1276 )
...
`elf-bin` is propagated to fesvr via the plusplus arg. Since #1240 , running
```
make sim elf-bin=path/to/elf
```
returns
```
terminate called after throwing an instance of 'std::runtime_error'
what(): could not open
+PRELOAD=path/to/elf (did
you misspell it? If VCS, did you forget +permissive/+permissive-off?)
```
As per the README, if preloading is needed, `make sim preload=path/to/elf` should be used
instead (https://github.com/openhwgroup/cva6/tree/master#memory-preloading ),
which sets `+PRELOAD=path/to/elf`
(6c89fda0da/Makefile (L249-L253)
2023-06-21 20:44:11 +02:00
MarioOpenHWGroup
d0a4c9f82e
Fix Questasim execution with rvfi_tracer ( #1240 )
2023-05-22 13:24:45 +02:00
Zbigniew Chamski
5ae46be23b
[C++ TB code] Upgrade C++ standard used. Clean up Makefile layout. ( #1235 )
...
* Makefile (CFLAGS): Use C++ 2017 standard. Fix whitespace.
(src): Fix whitespace.
($(dpi-library)/%.o): Do not add another (potentially conflicting) C++
standard option.
* ariane.core (verilator_options): Use C++ 2017 standard.
2023-05-22 11:02:07 +02:00
JeanRochCoulon
b0a3b90f85
Move ariane.sv from tb to src directory ( #1231 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-05-12 15:30:41 +02:00
MarioOpenHWGroup
8e39a17056
Adapt MMU to allow Questa compilation ( #1232 )
2023-05-11 23:05:35 +02:00
Robert Balas
c454a39ae3
Makefile: Fix vopt stage by forcing net compatible types for ports ( #1206 )
...
Fixes vopt stage for newer questasim versions
Co-authored-by: bluew <bluewww@users.noreply.github.com>
2023-05-04 16:25:55 +02:00
JeanRochCoulon
59a1df031c
Remove DROMAJO ( #1204 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-04-24 23:05:53 +02:00
JeanRochCoulon
a3e6521f97
HOTFIX: Make vcs-testharness work after #1158 merge
2023-04-24 08:33:11 +02:00
Umer Imran
45259cfb6a
LINT: Initial changes for Lint warnings removal ( #1158 )
2023-04-24 08:22:56 +02:00
JeanRochCoulon
c1df1da568
Declare rvfi package as common lib ( #1179 )
...
Merge this PR. The Thales CI will be failed before updating core-v-verif with corresponding modification.
2023-04-11 20:16:10 +02:00
JeanRochCoulon
710da10297
Remove RVFI_TRACE/RVFI_MEM ifdef verilog directive ( #1141 )
...
To allow to remove optionally ports, ifdef directive are kept in cva6_config package.
2023-04-11 07:49:59 +02:00
Nils Wistoff
09ed2de0df
Remove redundant axi_adapter.sv ( #1174 )
...
This module was moved to `core/cache_subsystem/axi_adapter.sv`
in #1127 .
2023-04-09 08:46:35 +02:00
JeanRochCoulon
d7491f4e28
Remove ifdef directives from IO cva6 module ( #1153 )
2023-04-04 07:52:10 +02:00
JeanRochCoulon
31948853c6
Replace WT_DCACHE define by CVA6ConfigCacheType localparam ( #1127 )
2023-03-21 14:18:18 +01:00
Nils Wistoff
cfef3e9c12
Makefile: Propagate CFLAGS from env ( #1042 )
...
Propagate the CFLAGS specified in the environment executing
the Makefile for DPI compilation. The current CFLAGS are
extended by the CFLAGS from the environment.
2023-02-07 23:33:26 +01:00
Nils Wistoff
3bc643e0e2
tb: Fix port width mismatch on AXI_USER_WIDTH and compile order for Questasim ( #1043 )
2023-02-02 08:10:49 +01:00
sébastien jacq
32abc1ccda
Add Fifo v3 to optimize fpga implementation in resource size ( #1032 )
2023-01-23 12:33:44 +01:00
Guillaume Chauvon
dc0ecfde0a
Change VCS option "Implicit wire no fanin" from WARNING to ERROR ( #1020 )
2022-12-15 11:56:59 +01:00
Zbigniew Chamski
17ccfc42f4
Vendorize corev_apu submodules referenced by CVA6 core. ( #1015 )
2022-12-13 12:20:36 +01:00
JeanRochCoulon
4b33e69a10
Use only one Flist for all configurations ( #1012 )
2022-12-13 09:31:26 +01:00
JeanRochCoulon
28c620a93a
fix dm package dependency ( #1011 )
2022-12-09 17:51:30 +01:00
JeanRochCoulon
c205a04c3b
Fix: move axi_adapter.sv file from core to corev_apu dir ( #1009 )
2022-12-09 16:35:37 +01:00
Zbigniew Chamski
8a5898dce4
Vendorize CVA6 core submodules (common_cells, FPU with related sub-modules) ( #1007 )
2022-12-09 11:07:12 +01:00
