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40 commits

Author SHA1 Message Date
khandelwaltanuj
3a389af151
added correct reset val (#2823)
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For cv64a60ax configuration
2025-03-12 15:19:15 +01:00
khandelwaltanuj
ab89beaebb
Adding a new configuration file for cv64a60ax and dv target RV64IMAFDC (#2761)
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A new configuration file and core v target is added to start working on a 64 bit CVA6 core.

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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-02-28 07:55:13 +01:00
Jalali
c19a3c1ace
Spike : mtvec doesn't support vectored mode for cv32a65x (#2729)
This is a spike fix for cv32a65x config.
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-22 23:42:47 +01:00
Munail Waqar
f7dd49efa5
Adding support for Scalar Crypto Extension (Bitmanip instructions for Cryptography, Zbkb) (#2653)
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Introduction
This PR adds support for Zbkb extension in the CVA6 core. It also adds the documentation for this extension. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will be followed by other PRs that will add complete support for the Zkn - NIST Algorithm Suite extension.

Implementation
Zbkb Extension:
Added support for the Zbkb instruction set. It essentially expands the Zbb extension with additional instructions useful in cryptography. These instructions are pack, packh, packw, brev8, unzip and zip.

Modifications
1. A new bit ZKN was added. The complete Zkn extension will be added under this bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set.
2. Updated the ALU and decoder to recognize and handle Zbkb instructions.

Documentation and Reference
The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for the Zbkb instruction was also added.

Verification
Assembly Tests:
The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior. The tests include:
pack-01.S
packh-01.S
packw-01.S
brev8-01.S
unzip-01.S
zip-01.S
2024-12-18 22:35:41 +01:00
Zbigniew Chamski
ed89c717f7
[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651)
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Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly.
2024-12-09 13:22:38 +01:00
Zbigniew Chamski
8a84f788d6
Increase Spike PMP granularity to 8. Update yaml spec files accordingly. (#2624)
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Update riscv-config spec files and Spike Yaml file for CV32A65X.

Bump CVV to change Spike default PMP granularity to 8 and to include corresponding Spike Yaml parameter.
2024-11-21 12:19:24 +01:00
JeanRochCoulon
a283d3eea2
Define cv32a60x configuration (#2608)
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2024-11-18 15:51:21 +01:00
slgth
ab2283c075
doc: keep documentation in sync with the code (#2558)
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Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
As of now, they are committed to the repository and can be out of sync with the code.

This PR removes them from the repository and freshly generates them from the code when building HTML files.

This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
2024-10-25 12:27:09 +02:00
Jean-Roch Coulon
9cfadbeded Create dedicated linker scripts for cv32a65x configuration. When another configuration is targeted, the default linker script is used (config/genxxx/linker/link.ld). When hwconfig is targeted, linker scripts are recopied into hwconfig directory.
Keep only one unique linker script: link.ldi. Remove test.ld file.
2024-10-23 18:24:38 +02:00
JeanRochCoulon
45eaace82b
Revert "Multicommits to shorten smoke-tests duration, to declare VLEN as para…" (#2564)
This reverts commit 0877e8e446.
2024-10-23 18:12:49 +02:00
JeanRochCoulon
0877e8e446
Multicommits to shorten smoke-tests duration, to declare VLEN as parameter, to improve coremark results, to implement spike.yaml/linker dedicated to 65x (#2563)
- FIX: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN
- Declare VLEN as new CVA6 parameter
- smoke-hwconfig: run with vcs-uvm and use return0 tests to speed-up CI light stage timing execution
- Use dedicated linker scripts for 65x configuration.
- Use dedicated spike.yaml for 65x configuration.
- Set BHTEntries=128, cache=WT, scoreboard entries=8 to improve Coremark and Dhrystone results
- Run 4 iterations of coremark to improve results
2024-10-23 17:56:06 +02:00
Zbigniew Chamski
2b3a82f2cc Fix CVV#2531: Make mie.MSIE and mip.MSIP RO-zero, prevent SW writes to mip. 2024-10-08 22:53:32 +02:00
Zbigniew Chamski
44072bfd83
[pmpcfg detailed spec] Add proposed CSR spec output. (#2522) 2024-10-02 23:32:12 +02:00
MarioOpenHWGroup
776e0137b6
[RVFI] Connect RVFI.intr to enable interrupts on TANDEM (#2475)
* [RVFI] Connect rvfi

* Lower verbosity to uvme_axi_covg
* Add unified_traps as a param for yaml
* Apply suggestions from code review

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>

---------

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2024-08-29 11:33:42 +02:00
MarioOpenHWGroup
6249bd1929
[TANDEM] CSR Params Refactor + CSR API (#2407) 2024-08-28 12:25:41 +02:00
Zbigniew Chamski
89eb77a249
[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem. Add workaround for AXI end-of-test asserts. (#2436) 2024-08-19 11:09:32 +02:00
Zbigniew Chamski
4e9abb284c
[cv32a65x] Remove unsupported Zifencei from riscv-config ISA string. (#2419) 2024-07-30 09:20:33 +02:00
Zbigniew Chamski
8dcdf8fb56
[riscv-config] Add memory map entry to platform schema and to CV32A65X platform spec. (#2411) 2024-07-26 23:50:51 +02:00
slgth
6a649d6515
docs: more fixes (#2412) 2024-07-26 23:49:41 +02:00
slgth
2249202769
docs: multiple fixes (#2409) 2024-07-26 15:27:42 +02:00
AbdessamiiOukalrazqou
a4583a6e4d
[gen_from_riscv_config] improve readme file to support debug spec (#2406) 2024-07-26 15:25:54 +02:00
Zbigniew Chamski
96b0508525
[riscv-config] Update PMP definitions in cv32q65x spec (#2401) 2024-07-25 22:06:51 +02:00
AbdessamiiOukalrazqou
b438a8ba8e
[gen_from_riscv_config] Improve the tool to support debug spec (#2398) 2024-07-25 20:07:45 +02:00
slgth
e9648eaf8c
Design documentation: AsciiDoc conversion (#2399) 2024-07-25 17:18:27 +02:00
AbdessamiiOukalrazqou
aa4ced4a8a
[gen_from_riscv_config] improve readme file and requirements file to support spike (#2380) 2024-07-22 18:04:53 +02:00
AbdessamiiOukalrazqou
5f8605838e
[gen_from_riscv_config] fix access issues for PMP registers, improve Factorization algorithm , improve csr_updater.yaml, add spike support (#2372) 2024-07-21 22:39:50 +02:00
Zbigniew Chamski
48ef515ba0
[Spike Yaml] Integrate Spike Yaml support. (#2304) 2024-07-11 08:37:37 +02:00
Moritz Schneider
246961b3c3
Increase max num PMPs to 64 (#2279) 2024-07-04 14:09:37 +02:00
AbdessamiiOukalrazqou
ee0847e30a
[gen_from_riscv_config] add custom-gen.yaml support / fix hyperlinks in csr design doc / improve readme/fix csr_updater.yaml (#2286) 2024-06-21 17:19:42 +02:00
Zbigniew Chamski
17ea49439f
[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. (#2270) 2024-06-19 12:08:15 +02:00
AbdessamiiOukalrazqou
3fccfba900
[gen_from_riscv_config]modify csr updater.py /fix-2191 , modify csr_updater.yaml (#2258) 2024-06-14 10:51:37 +02:00
Zbigniew Chamski
592487ffa0
[riscv-config] Align CV32A65X spec on adoc, cleanup defs. Fix CSR updater. (#2206) 2024-06-06 11:19:41 +02:00
Zbigniew Chamski
aa76752f18
Update riscv-config infra to better match expressivity needs of CV32A65X. (#2193) 2024-06-04 18:12:14 +02:00
AbdessamiiOukalrazqou
e0da6e3569
Fix access issues for reserved fields (#2187) 2024-06-03 15:54:10 +02:00
Zbigniew Chamski
c30c20bc2b
[riscv-config] HOTFIX: Regenerate output files for CV32A65X. (#2176) 2024-05-31 12:39:10 +02:00
Zbigniew Chamski
2534713373
[riscv-config] Fix issues in CV32A65X input spec and regenerate output. (#2165) 2024-05-29 17:35:47 +02:00
André Sintzoff
4df326e13c
utils.py: format and fix typos (#2163) 2024-05-29 09:37:46 +02:00
JeanRochCoulon
83191f4c3f
Change spike.yaml location (#2160) 2024-05-28 13:25:43 +02:00
AbdessamiiOukalrazqou
8fbfe3e57a
add gen from riscv config software (#2156) 2024-05-27 18:01:56 +02:00
Zbigniew Chamski
2240bd079b
Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X. (#2133) 2024-05-21 07:21:57 +02:00