Follow-up to the discussion on extending Linux support to the Ara vector processor.
* Main changes:
Add:
Add external MMU interface to share the MMU with the external accelerator.
Add avoid_neg() function used to clip negative numbers to zero. Useful for parametric array sizes and vector multipliers.
Modifications:
2 commit ports by default in cv64a6_imafdcv_config_pkg.
Change exception_t from localparam to param in cva6.sv.
Add parameters accelerator_req_t, accelerator_resp_t, acc_mmu_req_t, and acc_mmu_resp_t to cva6.sv.
Replace the fall-through register with a spill register in acc_dispatcher to decouple timing with the accelerator.
Decrease cache sizes in cv64a6_imafdcv_sv39_config_pkg.
Modify Bender.yml package name from ariane to cva6.
Add harmless code to prevent synthesizer tool from crashing when compiling csr_regfile.
* Collateral changes:
Fixes:
Guard some X-IF code lines with correct parameter in cva6.sv.
Parametrize the tracer interface with NrCommitPorts.
Add missing local dependencies to Bender.yml.
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This PR modifies some components in the CVA6 to fully support the WB mode of the HPDcache.
When on WB mode, there may be coherency issues between the Instruction Cache and the Data Cache. This may happen when the software writes on instruction segments (e.g. to relocate a code in memory).
This PR contains the following modifications:
The CVA6 controller module rises the flush signal to the caches when executing a fence or fence.i instruction.
The HPDcache cache subsystem translates this fence signal to a FLUSH request to the cache (when the HPDcache is in WB mode).
Add new parameters in the CVA6 configuration packages:
DcacheFlushOnInvalidate: It changes the behavior of the CVA6 controller. When this parameter is set, the controller rises the Flush signal on fence instructions.
DcacheInvalidateOnFlush: It changes the behavior of the HPDcache request adapter. When issuing a flush, it also asks the HPDcache to invalidate the cachelines.
Add additional values to the DcacheType enum: HPDCACHE_WT, HPDCACHE_WB, HPDCACHE_WT_WB
In addition, it also fixes some issues with the rvfi_mem_paddr signal from the store_buffer.
Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv.
Also reorders port maps to keep the same order as port declarations.
* Remove misaligned_ex computation: get it from outside
* Remove data and instr pmps, get match_execution from outside
* Get data and instr allow from outside
* Simplify fetch_instruction exception when instr not allow by pmp
* Simplify exception when data not allow by pmp, getting it from outside
* Apply verible format
* First public version of extracted pmp
* Integrate PMP fully outside MMU
* fix translation_valid and dtlb_ppn when no mmu
* Add pmp_data_if in needed file lists
* Fix exception tval when translation is enabled
* integrate no_locked assertions for pmp: now in blocking assignments to avoid raise condition in simulation
* Fix mixed assignment for no_locked_if
* Remove assertion no_locked from pmp: need clk and reset
* Apply verible format
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Co-authored-by: Olivier Betschi <olivier.betschi@fr.bosch.com>
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
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Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* [lsu] Add external store buffer pending stall signal
* [controller] Add external acc request pipeline flush signal
* [frontend] Do not increment commit pc on flush if commit stage is halted
* [acc_dispatcher] Add new store buffer stall and flush pipeline ctrl signals
* [acc_dispatcher] Add top module passable config type and parameter
* [cva6] Pass on missing CVA6Cfg parameter to acc_dispatcher
* Add load and store information to RVFI
* Add rs1 and rs2 information to RVFI
* Condition rvfi mem and rs1/rs2 information generation by RVFI_MEM
This add-on is requested by ISACOV and test termination.
