494 commits

Author	SHA1	Message	Date
Côme	339d3dd851	Increase code coverage on second ALU by removing branch logic (#2362)	2024-08-26 17:32:24 +02:00
Côme	064cec2066	fix missing ZCMP condition in commit stage to increasse Code Coverage (#2459)	2024-08-24 11:48:36 +02:00
Côme	76e5b40961	fix single-step which was x in cv32a65x config and fix mcycle for double commit (#2369)	2024-08-22 12:03:20 +02:00
André Sintzoff	051ba348f9	spyglass: remove WRN_1024 warnings (#2448)	2024-08-19 15:44:30 +02:00
André Sintzoff	e5618977d1	spyglass: move assignments in if clause as only used there (#2444)	2024-08-13 17:11:10 +02:00
André Sintzoff	af4e3744d4	spyglass: remove useless assignments (#2439)	2024-08-12 15:06:39 +02:00
MarioOpenHWGroup	4b51643826	TANDEM Configuration fixes (#2420)	2024-08-09 12:34:40 +02:00
JeanRochCoulon	ce4b25c51a	[HOT FIX] fix is_inside_execute (#2429) ... fix #2385	2024-08-02 08:42:11 +02:00
Asmaa Kassimi	12be3adb81	Solve some of W240 and W415a warnings increased by PMP entries (#2415)	2024-08-01 18:43:13 +02:00
Guillaume Chauvon	81671e39fa	Fixes and Update CVXIF non regression tests, regression and TB (#2424)	2024-08-01 16:06:24 +02:00
Guillaume Chauvon	211af02e5e	Separate RAW and WAW process to fix CVXIF with Superscalar (#2395)	2024-07-26 14:58:18 +02:00
Moritz Schneider	fd489a16fb	Fix off by one error in PMP length (#2394)	2024-07-25 12:08:53 +02:00
Asmaa Kassimi	631513eda8	Add RVU condition to increase coverage (#2396)	2024-07-25 12:03:38 +02:00
Somya Dashora	1e48237a7a	Update csr_regfile.sv to fix #2373 (#2374)	2024-07-25 09:54:13 +02:00
CoralieAllioux	335c91cc08	[Xcelium flow] Xrun compile fixes (#2389)	2024-07-25 07:37:43 +02:00
Asmaa Kassimi	4c48a60804	increase condition coverage in lsu, issue and commit stages (#2391)	2024-07-25 07:37:21 +02:00
Côme	4ff16f9da3	set WtDcacheWbufDepth to 8 (#2390)	2024-07-24 23:54:26 +02:00
Asmaa Kassimi	14be0af7f0	solve simple lint errors (#2388)	2024-07-24 12:09:25 +02:00
JeanRochCoulon	04ebfbd713	Disable PMA execute and nonidempotent features (#2385)	2024-07-23 15:57:22 +00:00
Côme	2acf5ba407	fix ex_stage synthesis (#2384)	2024-07-23 14:09:01 +02:00
Côme	4a223bee46	decorrelate instr and addr depths in IQ (#2375)	2024-07-22 14:22:56 +02:00
Asmaa Kassimi	8aa0f634f6	condition load and store modules (#2349)	2024-07-13 09:32:51 +02:00
Côme	0cbd894a7a	update port and config docs (#2363)	2024-07-12 17:00:36 +02:00
jzthales	71653038d7	Doc lsu (#2359)	2024-07-12 16:49:02 +02:00
Guillaume Chauvon	8fa590b5c3	CVXIF 1.0.0 (#2340)	2024-07-12 10:53:18 +02:00
Côme	5fcc39dbee	remove round interval (#2353)	2024-07-11 17:35:03 +02:00
Côme	2dcb7417b4	make cv32a65x superscalar (#2348)	2024-07-10 23:33:49 +02:00
Asmaa Kassimi	214444cc93	csr_regfile lint error fix (#2346)	2024-07-10 13:13:26 +02:00
Asmaa Kassimi	d9a7fdb836	condition branch_unit and alu (#2342)	2024-07-10 11:02:18 +02:00
Côme	37d93a3758	superscalar: do not issue CSR with another instruction (#2329)	2024-07-05 23:49:44 +02:00
Moritz Schneider	6044454a07	Fix index calculation for PMPCFG CSR write logic (#2330)	2024-07-05 22:56:27 +02:00
Asmaa Kassimi	67dba2cad3	condition csr_regfile.sv (#2310)	2024-07-05 14:14:01 +02:00
Côme	4df49a6b0f	superscalar: make SuperscalarEn a CVA6Cfg attribute (#2322)	2024-07-05 14:09:48 +02:00
Moritz Schneider	246961b3c3	Increase max num PMPs to 64 (#2279)	2024-07-04 14:09:37 +02:00
Asmaa Kassimi	3874c41320	fix lint errors in csr_regfile.sv (#2306)	2024-07-02 15:36:04 +02:00
Côme	636e6aff47	superscalar add second ALU (#2303)	2024-06-30 18:24:11 +02:00
Guillaume Chauvon	ced13a56b1	Fix typo on Bitmanip comment (#2300)	2024-06-28 15:01:50 +02:00
JeanRochCoulon	21383ce16d	Fix mstatus.mpp in relation to the possible legal values (#2285)	2024-06-21 17:27:48 +02:00
Moritz Schneider	fe1a19fca7	Fix WARL behavior of MPP (#2283) ... Related to #2274	2024-06-21 14:38:57 +02:00
André Sintzoff	21733e55d7	decoder.sv: add checks for some B instructions (fix #2276) (#2282)	2024-06-21 10:54:10 +02:00
Côme	96ae8ed223	superscalar: allow speculative instructions (#2278)	2024-06-20 15:55:56 +02:00
Michael Platzer	318be6dcde	Use correct fault type for VLSU overflow (#2273)	2024-06-19 21:31:00 +02:00
Cesar Fuguet	9df64701bd	Update submodule core/cache_subsystem/hpdcache (#2265)	2024-06-18 11:54:35 +02:00
slgth	e3943f5913	cv64a6_mmu: set NrPMPEntries to 16 (fixes #2244) (#2248)	2024-06-14 10:05:35 +02:00
JeanRochCoulon	cb6211bbb8	Remove cv32a6_embedded configuration (#2246)	2024-06-14 08:30:17 +02:00
AngelaGonzalezMarino	8164828913	Fix instruction realign when C extension is not used (#2241)	2024-06-13 11:17:25 +02:00
Akiho Kawada	bc7149adc7	refactor hpdcache_cache_subsystem module code to ease reutilization (#2173)	2024-06-11 23:12:30 +02:00
JeanRochCoulon	4391fc4b14	Use cv32a6_imac_sv32 to generate FPGA bitstream (#2229)	2024-06-11 16:25:07 +02:00
André Sintzoff	546a8c26da	csr_regfile.sv: if no U-mode, mstatus.tw is read-only 0 (fix #2228) (#2233)	2024-06-11 15:08:28 +02:00
JeanRochCoulon	2266f75f2d	MTVAL is read-only zero when TvalEn = 0 (#2231)	2024-06-11 11:22:41 +02:00