André Sintzoff
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afb3265296
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csr_regfile.sv: if no U-mode, mcounteren does not exist (fix #2221) (#2227)
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2024-06-10 21:42:00 +02:00 |
|
JeanRochCoulon
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7ccf82ce76
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Add param to enable/disable Zihpm and Zicntr extensions for 65x (#2208)
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2024-06-10 15:14:03 +02:00 |
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JeanRochCoulon
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dc000d6c37
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Define a new param to constraint mtvec to be in direct mode only (#2226)
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2024-06-10 11:59:54 +00:00 |
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Côme
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eac60af1a9
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superscalar: add a second issue port (#2209)
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2024-06-09 20:47:09 +02:00 |
|
Guillaume Chauvon
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a5152b03a5
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Add support for cv32a65x dedicated synthesis (#2178)
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2024-06-04 10:58:09 +02:00 |
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AngelaGonzalezMarino
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3e907d625f
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fix tval in mmu (#2124)
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2024-05-31 15:26:33 +02:00 |
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Cyprien Heusse
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46e9d5a7fc
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32 bits WB cache (#2170)
|
2024-05-30 18:47:39 +02:00 |
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MarioOpenHWGroup
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d714d833cb
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Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044)
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2024-05-30 15:57:58 +02:00 |
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JeanRochCoulon
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8630458370
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Parametrization: Use CVA6Cfg.WtDcacheWbufDepth in place of DCACHE_WBUF_DEPTH (#2166)
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2024-05-30 12:26:58 +02:00 |
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dependabot[bot]
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691c480aea
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Bump core/cache_subsystem/hpdcache from 57c82d3 to 32407cb (#2157)
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2024-05-27 23:06:50 +02:00 |
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slgth
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9f4b2f7179
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New target with MMU: cv64a6_mmu (#2149)
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2024-05-24 13:39:00 +02:00 |
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AngelaGonzalezMarino
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be14a84165
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Add the condition for updating the tlb only after a miss is incurred (#2120)
|
2024-05-23 11:50:37 +02:00 |
|
AngelaGonzalezMarino
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f8b07f09ab
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Invalid pte reserved (#2123)
|
2024-05-23 11:50:09 +02:00 |
|
Cyprien Heusse
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e823d836f3
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Fix bug when killing WB cache request (#2142)
|
2024-05-22 23:40:11 +02:00 |
|
JeanRochCoulon
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73d3814fbd
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Continue parametrization: as two localparams are not more used by UVM, remove them (#2141)
|
2024-05-22 18:13:28 +02:00 |
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MarioOpenHWGroup
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b48a2bb63d
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[CSR] Fix bits when RVS and RVU not available (#2074)
|
2024-05-22 15:54:51 +02:00 |
|
AngelaGonzalezMarino
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9142fdd03a
|
integrate unified mmu with H extension (#1958)
|
2024-05-16 00:24:50 +02:00 |
|
JeanRochCoulon
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821e2ebc3f
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Remove localparam related to hpdcache in 65x config (#2115)
|
2024-05-16 00:20:04 +02:00 |
|
Cesar Fuguet
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cd241cb387
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hpdcache: update HPDcache to support parametrization (#2059)
|
2024-05-15 12:28:36 +02:00 |
|
JeanRochCoulon
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4c58b50045
|
CV32A65X: Switch from WT to HPDCache (#2097)
* switch from WT to HPDCache for CV32A65X configuration
* Comment AXI agent asserts which are not compatible with HPDCache
|
2024-05-15 07:37:40 +00:00 |
|
JeanRochCoulon
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dd763b4f4c
|
Rename FpuEn into RVF (#2109)
|
2024-05-15 09:16:44 +02:00 |
|
Asmaa Kassimi
|
807ed7825c
|
Add Supervisor condition under Interrupt control and remove else condition. (#2098)
|
2024-05-12 21:02:57 +02:00 |
|
Florian Zaruba
|
9f40ad57cb
|
Make D independent on xlen (#2005)
A 64-bit core might very well support just single-precision.
|
2024-05-12 20:15:50 +02:00 |
|
Bruno Sá
|
96874d1ccb
|
fix hypervisor configs (#2083)
|
2024-04-29 14:58:18 +02:00 |
|
Côme
|
261e5d3192
|
superscalar: add issue port to scoreboard (#2081)
|
2024-04-26 16:04:04 +02:00 |
|
Côme
|
779927485d
|
superscalar: duplicate decode stage (#2077)
|
2024-04-26 12:09:42 +02:00 |
|
JeanRochCoulon
|
3ecabdb95a
|
Cvfpu from vendor to submodule (#2070)
|
2024-04-23 14:54:42 +02:00 |
|
MarioOpenHWGroup
|
8a9d7a832b
|
Fix RVFI always_ff blocks (#2053)
|
2024-04-18 10:06:34 +02:00 |
|
Florian Zaruba
|
377b0de154
|
Fix SuperScalar config and add CVA6Cfg to first pass decoder (#2047)
* Add `CVA6Cfg` to first pass decoder
* Fix `verilator` `SELRANGE` warnings
* Update core/decoder.sv
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
* Update core/cva6_accel_first_pass_decoder_stub.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/decoder.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/frontend/instr_queue.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
---------
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
|
2024-04-17 16:34:08 +02:00 |
|
MarioOpenHWGroup
|
71ef48804a
|
[RVFI] Optimize CSRs (#1999)
|
2024-04-15 16:29:07 +02:00 |
|
JeanRochCoulon
|
e1ee77e02d
|
define WtDcacheWbufDepth as cva6 parameter and fix rvfi.svh (#2040)
|
2024-04-15 15:05:30 +02:00 |
|
Moritz Schneider
|
0a160c9294
|
Fix reserved value in MPP (#2035)
|
2024-04-12 11:13:17 +02:00 |
|
JeanRochCoulon
|
5df5a5c247
|
Define InstrTlbEntries, DataTlbEntries, cfg.NrLoadPipeRegs, NrStorePipeRegs, DcacheIdWidth as CVA6 parameters (#2034)
|
2024-04-12 09:06:35 +02:00 |
|
André Sintzoff
|
9bd5667992
|
decoder.sv: fix ZEXT.H instruction (fix #1758, #1975, #2010) (#2032)
- add missing ZEXT.H for RV64
- fix ZEXT.H for RV32: bit[24:20] shall be 0
|
2024-04-11 16:38:11 +02:00 |
|
JeanRochCoulon
|
527a989542
|
Clean-up 65x config_pkg.sv file by removing the localparams (#2031)
|
2024-04-11 11:29:31 +02:00 |
|
Florian Zaruba
|
ecd6ed6b6b
|
Move DCacheType to config struct (#2025)
|
2024-04-10 23:26:21 +02:00 |
|
Moritz Schneider
|
fa2cea2d65
|
Fix PMPCFG WARL behavior (#2019)
|
2024-04-09 16:40:00 +02:00 |
|
Côme
|
1c529d68ce
|
superscalar: return 2 instructions from instruction queue (#2022)
|
2024-04-09 16:39:24 +02:00 |
|
JeanRochCoulon
|
f4ec364bf4
|
Fix MIE CSR described in #2004 and #2008 Github issue (#2017)
|
2024-04-08 19:54:55 +02:00 |
|
Moritz Schneider
|
90d780eb14
|
Fix PMP CSR locked behavior (#2015)
|
2024-04-08 14:01:14 +02:00 |
|
JeanRochCoulon
|
80e6d7cffc
|
Verible reformat (#2014)
|
2024-04-08 11:26:08 +02:00 |
|
Côme
|
ec44b22920
|
superscalar: fetch 64 bits (#2013)
|
2024-04-08 11:25:39 +02:00 |
|
Cesar Fuguet
|
83a5b05752
|
hpdcache: update submodule (#2009)
|
2024-04-05 18:52:10 +02:00 |
|
Florian Zaruba
|
38e8c059b2
|
Parameterization and other fixes for downstream project (#1950)
* Bender fixes and switch to `cva6_fifo_v3`
* cfg: Fix verilator warnings
* Bender: Fix yml
* acc_dispatcher: Add `csr_addr_i`
* parameterization: Fox AXI_USER_EN warning
* wb_cache: Fix Verilator Lint warnings
* cva6_fifo_v3: Add to Flist
* parameterization: Address review concerns
* Switch to `cva6_fifo_v3`
* tracer: Remove tracer interface
The interface made a bunch of problems with the
typedefs so I've removed it.
---------
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
|
2024-04-05 13:02:18 +02:00 |
|
Côme
|
f886713754
|
User config generator becomes a Python tool to work with configs (#2003)
|
2024-04-04 15:56:29 +02:00 |
|
JeanRochCoulon
|
4423feb06a
|
Rename ZiCondExtEn and FPGA_EN parameters (#1992)
|
2024-04-02 15:37:58 +02:00 |
|
JeanRochCoulon
|
8d6c1f709f
|
Modify the variable order inside the cva6_user_cfg_t (#1971)
Modify the variable order inside the cva6_user_cfg_t to gather extension params together and micro-architecture params together
|
2024-03-28 15:19:49 +01:00 |
|
JeanRochCoulon
|
64273ca4af
|
update Design Doc after bumping H extension (#1968)
|
2024-03-28 09:32:59 +01:00 |
|
MarioOpenHWGroup
|
08d098bf51
|
[RVFI] Change CSR implementation (#1952)
|
2024-03-25 12:15:18 +01:00 |
|
Yannick Casamatta
|
5bc063131a
|
csr_regfile.sv: use CVA6Cfg.ASID_WIDTH instead of AsidWidth (fix cv64a6) (#1951)
|
2024-03-25 11:51:12 +01:00 |
|