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247 commits 16 branches 13 tags 288 MiB
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Author SHA1 Message Date
Florian Zaruba
18090c8c1c Fix issue #31 2017-05-12 19:21:42 +02:00
Florian Zaruba
b3173ab6f2 Put flush to sequential process 2017-05-12 14:54:21 +02:00
Florian Zaruba
03cc04f96a Change flush assignment in scoreboard 2017-05-12 14:51:13 +02:00
Florian Zaruba
ea8fde0a3f Move branch comparisons to branch engine 2017-05-12 12:22:56 +02:00
Florian Zaruba
5ffb9ef36c 🐛 Fix remove ALU operators 2017-05-12 10:42:03 +02:00
Florian Zaruba
74c33bf1ba Removing unnecessary branch operators 2017-05-12 00:14:48 +02:00
Florian Zaruba
0a81031e5a Add IF <-> ID acknowledge signal 2017-05-11 20:31:14 +02:00
Florian Zaruba
5ec741da4c 🐛 Branching in frontend works now 2017-05-11 18:18:13 +02:00
Florian Zaruba
742fb2b307 Basic branching in place 2017-05-11 13:26:20 +02:00
Florian Zaruba
2b790db79b Add support for compressed branches 2017-05-11 11:11:51 +02:00
Florian Zaruba
d624a4163c Increase prefetch depth from 3 to 4 2017-05-11 10:57:26 +02:00
Florian Zaruba
b0ebde437c 💚 Fix scoreboard underflow bug 2017-05-11 10:46:53 +02:00
Florian Zaruba
0f1e08fb91 🐛 Fixes in scoreboard, issue and branches 2017-05-10 20:09:03 +02:00
Florian Zaruba
61afdb9e30 Complete branch prediction path through IF, ID, EX 2017-05-10 15:08:39 +02:00
Florian Zaruba
6b9ba5b314 📝 Add some further comments on resolved branches 2017-05-09 18:49:34 +02:00
Florian Zaruba
fac352baaf Add unresolved branch handling 2017-05-09 18:44:09 +02:00
Florian Zaruba
1e76a021ce Rework decode logic for new branch engine 2017-05-09 18:06:09 +02:00
Florian Zaruba
a07a8f0a00 Integrate branch prediction, fix #2 2017-05-09 17:16:11 +02:00
Florian Zaruba
5a3c0e3fe2 Implement branching logic and address calc 2017-05-09 16:09:05 +02:00
Florian Zaruba
1fa1e8c109 Add branch decode logic in decoder 2017-05-09 10:58:03 +02:00
Florian Zaruba
8bf1f1efb9 Instantiate pcgen and controller 2017-05-08 19:18:11 +02:00
Florian Zaruba
227a1b25eb Include pcgen and controller stub 2017-05-08 18:30:22 +02:00
Florian Zaruba
8dfd373669 🐛 Fix wrong fu ready output assignment 2017-05-08 18:11:13 +02:00
Florian Zaruba
6cb97a53c9 Add basic assembly test 2017-05-08 17:59:48 +02:00
Florian Zaruba
fc6f5356fb Add different slave modes to mem_if 2017-05-08 17:02:59 +02:00
Florian Zaruba
ba56248f18 Add core test sequence, simply waiting for now 2017-05-08 15:18:53 +02:00
Florian Zaruba
7fc07259ab Merge branch 'initial-dev' of iis-git.ee.ethz.ch:floce/ariane into initial-dev 2017-05-08 15:02:37 +02:00
Florian Zaruba
7ab0e0de2f Start implement UVM core tb 2017-05-08 15:02:20 +02:00
Florian Zaruba
b3544816e4 Remove simulation warnings 2017-05-08 12:41:20 +02:00
Florian Zaruba
a813180137 📝 Add pipeline diagram to diagram section 2017-05-07 23:15:10 +02:00
Florian Zaruba
321ac41cd5 TLB lookup now features a separate register stage 2017-05-07 22:53:37 +02:00
Florian Zaruba
c62683ed32 👾 Fix synthesis warnings 2017-05-07 22:52:25 +02:00
Florian Zaruba
442db02e6f 👾 Remove timing loop in exception hdl 2017-05-07 17:33:12 +02:00
Florian Zaruba
ab08a4e228 📝 Add further clarification on timings 2017-05-07 15:05:01 +02:00
Florian Zaruba
a752a78cfd 📝 Add timing diagram for memory interface 2017-05-07 13:09:05 +02:00
Florian Zaruba
5fe1d7f067 📝 Add the ability to display timing diagrams 2017-05-07 12:37:18 +02:00
Florian Zaruba
4658c6f182 👕 Remove linter warnings in CSR file 2017-05-06 20:05:12 +02:00
Florian Zaruba
65914ea35a Implement LSU and CSR commit signal from commit 2017-05-05 18:50:11 +02:00
Florian Zaruba
0f80a6d211 Implement CSR instruction in decoder 2017-05-05 17:51:28 +02:00
Florian Zaruba
b0040c754d Instantiated CSR File and wiring control 2017-05-05 15:26:27 +02:00
Florian Zaruba
556a78bf9c 💚 Rename lsu_commit signal in lsu tb 2017-05-05 14:36:59 +02:00
Florian Zaruba
2430599328 Instantiate csr address buffer in ex 2017-05-05 12:42:03 +02:00
Florian Zaruba
decde29bb3 Wiring cleanup in id stage 2017-05-05 12:26:23 +02:00
Florian Zaruba
c62a6fc642 Add CSR buffer which holds the CSR addr for commit 2017-05-05 11:43:13 +02:00
Florian Zaruba
4b75332d10 📝 Update documentation with CSR FU 2017-05-05 11:28:55 +02:00
Florian Zaruba
9ea677b843 Fix issue #8 2017-05-05 11:06:37 +02:00
Florian Zaruba
fdebfb7316 Add CSR output assignments and delegation ctrl 2017-05-04 22:11:08 +02:00
Florian Zaruba
6c4a9c2452 📝 Add some information about exception handling 2017-05-04 19:56:52 +02:00
Florian Zaruba
2fe5cbad49 Add additional exception information to sbe 
Moved PC from exception to scoreboard entry as we have the entry
available in the commit stage where we take the exception. Also add the
additional exception information which we need to set the s/mval field.
 2017-05-04 19:51:53 +02:00
Florian Zaruba
e683824b2a CSR regfile implemented, compliant to priv 1.10 2017-05-04 19:31:14 +02:00