JeanRochCoulon
c76b29a887
Update after parametrization changes ( #1943 )
2024-03-19 11:09:46 +01:00
Rohan Arshid
b8ca8588cf
Updated Zcmp extension user guide and specification document ( #1930 )
2024-03-15 18:33:01 +01:00
Rohan Arshid
94f6528e1f
[Docs] Add Zcmp Instructions in CVA6 user guide and requirement specifications ( #1927 )
2024-03-13 22:52:44 +01:00
JeanRochCoulon
57f062bd85
Add Caches submodule description in Design Doc ( #1923 )
2024-03-12 17:40:05 +01:00
JeanRochCoulon
378144ddc4
03 doc is deprecated ( #1922 )
...
GitHub Issues report 03 doc limitations. As it is not the main design document, we would like to notify that it is deprecated.
2024-03-12 16:36:27 +00:00
JeanRochCoulon
301f18a5f4
Improve FRONTEND description ( #1914 )
2024-03-11 12:52:35 +01:00
JeanRochCoulon
b3ae6e9362
Revert MMU ( #1890 )
...
* Revert "fix vcs simulation errors regarding hypervisor extension code (#1889 )"
This reverts commit 5ff5f164fb#1881 )"
This reverts commit 6a5863e71a#1876 )"
This reverts commit 9fb5db2555
2024-03-05 16:44:40 +01:00
AngelaGonzalezMarino
6a5863e71a
Mmu user manual ( #1881 )
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* user manual update mmu v0
* Include information for hypervisor extension use. Fix issue in satp mode bits.
* Remove old text
2024-03-05 13:50:45 +01:00
JeanRochCoulon
483ef90127
Update frontend module description ( #1882 )
2024-03-04 23:18:27 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document ( #1865 )
2024-02-23 23:09:11 +01:00
JeanRochCoulon
b4c287a18e
Design Document, add ID_STAGE description ( #1832 )
2024-02-16 16:17:46 +01:00
JeanRochCoulon
0f2b137984
Populate instruction chapter in CV32A65X Design Document ( #1820 )
2024-02-12 09:58:02 +01:00
Jérôme Quévremont
ef3bb06fbf
Adding configuration-specific CSR doc ( #1766 )
2024-02-09 13:39:48 +01:00
JeanRochCoulon
3f8649ec7e
Table builder for specification ( #1814 )
2024-02-08 10:54:47 +01:00
JeanRochCoulon
9d0c700f42
port_builder generates the table of ports ( #1805 )
2024-02-06 12:06:13 +01:00
André Sintzoff
dc634c61de
doc: update MVENDORID CSR value ( fix #1735 ) ( #1753 )
2024-01-10 11:30:48 +01:00
JeanRochCoulon
2708df998d
Rename cva6 ( #1723 )
2024-01-02 12:05:07 +01:00
Jérôme Quévremont
6e79e20cc6
UM: Part number + reshuffled Zb* RV32/RV64 instructions ( #1733 )
2023-12-21 17:23:14 +01:00
Jérôme Quévremont
5716b378da
Integrated Zb* in user manual (index.rst) ( #1728 )
2023-12-20 08:39:10 +01:00
Gull Ahmed
b3139eaae0
update Zb* docs ( #1721 )
2023-12-19 17:46:23 +01:00
Jérôme Quévremont
4103b2ccdc
Changing part number in user manual ( #1718 )
2023-12-18 16:32:30 +01:00
Jérôme Quévremont
ad570000b3
Remove fixed-time division (ISA-110) ( #1670 )
...
After further investigation, the feature is not needed for security application.
For safety applications, variable-time division is only one of several sources of unpredictability and it does not make no real sense to fix it.
2023-12-15 14:52:10 +01:00
JeanRochCoulon
5e9cb5d64e
Designdoc ( #1713 )
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* rename csr files
* Revisit the design specification skeleton
2023-12-15 14:51:32 +01:00
Florian Zaruba
344c1db4b8
Clarify pmpcfgX on illegal write combination ( fixes #1694 ) ( #1711 )
2023-12-14 15:48:40 +01:00
Jérôme Quévremont
6e41bc8b52
Updated user manual to address several configuration (second pass) ( #1696 )
2023-12-13 10:10:31 +01:00
Jérôme Quévremont
98c776dc2d
Updated user manual to address several configuration (first pass) ( #1685 )
2023-12-13 10:08:40 +01:00
JeanRochCoulon
9952bce6a6
Add embedded csr description and CSR table list ( #1662 )
2023-12-06 09:16:21 +01:00
Mike Thompson
73cd1c5eeb
Add the Zc* ISA to "Applicable Specifications" ( #1615 )
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* Add the Zc* ISA to "Applicable Specifications"
* Update cva6_requirements_specification.rst: embedded part number
* Change D and I cache information
---------
Co-authored-by: Jérôme Quévremont <jerome.quevremont@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2023-11-23 09:41:08 +01:00
André Sintzoff
30cf669a32
CSR user manual: add precise trap description ( fix #1217 ) ( #1646 )
2023-11-21 19:05:50 +01:00
Côme
758511fd79
docs: fix example of OoO write-back to scoreboard ( #1621 )
...
Multiplication takes two cycles (1 cycle latency) and ALU takes one
cycle (no latency). They share the same writeback port so it is not
possible to issue an ALU instruction just after a MUL. So the example
is wrong, but it is okay if we replace MUL by LOAD as it uses another
write-back port.
Fix #1106
2023-11-13 10:59:26 +01:00
Abdul Wadood
9e47cc6947
removed c.zext.w from rv32 spec ( #1563 )
...
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
2023-10-23 14:55:05 +00:00
Abdul Wadood
43c12816f6
[DOCS] Add Zcb Instructions in CVA6 user guide and requirement specification ( #1536 )
2023-10-19 16:22:46 +02:00
Pascal Cotret
f0bd20b78c
fix most of sphinx warnings ( #1509 )
2023-10-08 14:42:57 +02:00
YazanHussnain-10x
6eea97f60e
Update CVA6 Architecture overview Figure ( #1488 )
2023-10-02 09:02:33 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
YazanHussnain-10x
67ac2566da
Add design documentation of MMU SV32 ( #1412 )
2023-09-27 10:58:29 +02:00
Fatima Saleem
4fb073f91c
[Docs] Adding Zicond in user and requirement specs ( #1444 )
2023-09-18 23:39:26 +02:00
Asim Ahsan
0aec609196
Update programmers view ( #1259 )
2023-08-23 12:33:39 +02:00
Jérôme Quévremont
8813d96995
[Skip CI] CV-X-IF user guide: editorial changes. ( #1331 )
2023-08-23 12:31:08 +02:00
Guillaume Chauvon
a052d4f2d5
Add CVXIF chapter in user's guide ( #1289 )
...
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2023-08-09 15:49:36 +02:00
Mohamed Aziz Frikha
6ce4705ade
Fix the reset value of MISA in user manual ( fix #1048 ) ( #1330 )
...
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-08-08 17:54:59 +02:00
Mohamed Aziz Frikha
853fb4bee5
[DOC] Adding legal values to MIP, MIE, SIP and SIE registers ( #1326 )
...
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-08-03 09:34:23 +02:00
Mohamed Aziz Frikha
b928fdfade
Adding Legal values to MTVEC and STVEC registers to fix #1060 and #1079 issues ( #1325 )
...
* Adding Legal values to MTVEC and STVEC registers to fix #1060 and #1079 issues
* Updating MTVEC and STVEC description
---------
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-31 11:45:00 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory ( #1318 )
...
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2023-07-28 08:32:48 +02:00
Mohamed Aziz Frikha
716bc7175a
Adding RISC-V behavior (WARL, WLRL, WPRI) to the specification of CSRs ( #1314 )
...
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-20 19:09:34 +02:00
André Sintzoff
9b4b6abe61
Traps_Interrupts_Exceptions.rst: update chapter ( #1291 )
...
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-07-20 10:56:09 +02:00
Mohamed Aziz Frikha
5fff2244e4
Adding Fields VS and UBE to MSTATUS in Specification to solve issue #1131 ( #1308 )
...
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-19 17:24:12 +02:00
Florian Zaruba
7068948245
Add first draft on PMA region ( #1295 )
...
* Add first draft on PMA region
* Address code review comments
2023-07-04 15:28:44 +02:00
Mohamed Aziz Frikha
3cb54a1623
Changing Addresses of ICACHE and DCACHE to solve #1202 issue. ( #1290 )
...
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-01 17:27:57 +02:00
Mohamed Aziz Frikha
71e7019834
Adding WPRI in spec : register MSTATUS ( #1257 )
...
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-06-08 22:42:04 +02:00
