34 commits

Author	SHA1	Message	Date
Jalali	212c14e4b4	CSR verification : modify coverage based on new specification (#2261)	2024-06-14 14:01:23 +02:00
Mathieu Gouttenoire	3d00079c19	Prepare for LLVM (#2251)	2024-06-14 11:12:03 +02:00
JeanRochCoulon	cb6211bbb8	Remove cv32a6_embedded configuration (#2246)	2024-06-14 08:30:17 +02:00
AEzzejjari	1c828c0a16	Connect the new AXI agent with CVA6 (#2182)	2024-06-03 14:42:37 +02:00
xiaoweish	4e9c6ac9a3	Update testlist yaml with #2073 PR using yaml anchor/alias (#2146)	2024-05-23 11:25:04 +02:00
JeanRochCoulon	dd763b4f4c	Rename FpuEn into RVF (#2109)	2024-05-15 09:16:44 +02:00
Jalali	130a526f3b	ISA : Cover zext with instr[24:20] != 0 (#2085)	2024-04-30 17:02:37 +02:00
xiaoweish	3919e79f8f	Implement YAML anchor/alias for streamlined testlist structure (#2073)	2024-04-28 23:00:22 +02:00
Jalali	5971fc755a	ISA coverage status (#2066)	2024-04-22 17:51:28 +02:00
André Sintzoff	1e93175dd4	testlists for cv32a65x: add files (#2037)	2024-04-12 17:47:03 +02:00
Côme	f886713754	User config generator becomes a Python tool to work with configs (#2003)	2024-04-04 15:56:29 +02:00
valentinThomazic	3dc1f23a9d	Support Spike Parameters in cva6.py and bump core-v-verif (#1976)	2024-04-02 10:26:25 +02:00
MarioOpenHWGroup	08d098bf51	[RVFI] Change CSR implementation (#1952)	2024-03-25 12:15:18 +01:00
MarioOpenHWGroup	62bdf11594	Bump core-v-verif d94f0de and fix questa simulator (#1915)	2024-03-21 19:02:41 +01:00
Jalali	6851499b18	Add directed Tests for jump instructions (#1933)	2024-03-15 15:16:21 +00:00
Rohan Arshid	c827c3b770	Zcmp extension support (#1779)	2024-03-13 11:37:49 +01:00
Jalali	9c4a3c37d6	Remove mcountinhibit from csr_test and UVM env (#1863)	2024-02-21 19:13:57 +01:00
Jalali	5dd04829e3	ISA functional coverage : Add directed tests (#1855)	2024-02-21 09:31:54 +01:00
AEzzejjari	5e80c104c9	AXI agent: Connect the the new AXI agent (#1817)	2024-02-18 23:31:44 +01:00
Jalali	3d7e417bce	Functional coverage : Add cross to illegal and exception coverage models (#1839)	2024-02-18 23:30:11 +01:00
MarioOpenHWGroup	c7f0eaf0d8	Bump verif/core-v-verif from fd68dfd to c7d2077 (#1828)	2024-02-13 14:20:21 +01:00
Jalali	c2d9d4b283	MTVAL : Remove MTVAL CSR from CVA6 UVM environment (#1788)	2024-01-26 16:47:15 +01:00
Jalali	179084315f	ISACOV : Update seq Directed test, and remove failing tests from regression (#1787)	2024-01-26 15:02:31 +01:00
Jalali	4cd5c4a7e8	Add overflow counter test & fix reset value (#1746)	2024-01-05 13:29:48 +01:00
Jalali	447d01a163	[Verif] Clear MIP CSR to avoid trapping in CSR tests (resume #1660) (#1661)	2023-11-29 15:09:10 +01:00
Jalali	6254dfa721	Clear MIP CSR to avoid trapping (#1660)	2023-11-29 13:55:50 +01:00
MarioOpenHWGroup	220f534b6d	Spike Tandem Implementation using VCS simulator (#1561)	2023-11-09 19:29:24 +01:00
Jalali	c31ebcd321	Add CSRs tests for embedded config (#1601)	2023-11-07 14:09:08 +01:00
Fatima Saleem	38b1da26c3	adding bitmanip and atomic arch-tests (#1560)	2023-10-20 16:03:12 +02:00
Côme	e8022778b7	ci: reorganize jobs (#1517)	2023-10-09 22:35:23 +02:00
sai krishna pidugu	c6877587ea	CV32A6 CSR Access Verification (#1380)	2023-09-28 14:11:55 +02:00
Jalali	e32e3871df	ISACOV : Add test for sequential hazard instruction (#1471)	2023-09-26 16:34:26 +02:00
Ammar Khan	72143ef0a9	SV32-DV-Plan Execution (#1376)	2023-09-21 21:03:07 +02:00
Côme Allart	736be43a73	move files to a verif directory	2023-09-07 09:50:50 +02:00