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Author SHA1 Message Date
Andreas Traber
153c009090 Strip trailing whitespace 2016-04-29 11:07:53 +02:00
Andreas Traber
b227723ff5 Add all halt to core 2016-04-29 10:57:05 +02:00
Pasquale Davide Schiavone
cb97227440 Fix wfi + sleep in debug mode 2016-04-29 10:23:25 +02:00
Andreas Traber
df014ec3ba Fix issue #1 on github, byte address should always be 0 2016-04-26 16:56:42 +02:00
Andreas Traber
101ef713f1 Update core_id and cluster_id widths everywhere 2016-04-21 18:32:35 +02:00
Andreas Traber
52a6c2002e Change size of core and cluster id 2016-04-21 16:33:27 +02:00
Andreas Traber
1284e315ec Some fixes to debug 2016-04-21 15:59:10 +02:00
Andreas Traber
57b77ba394 Fix some smallish issues 2016-04-20 14:17:09 +02:00
Andreas Traber
5e30493243 Started work on MMIO debug 2016-04-20 10:49:48 +02:00
Andreas Traber
74fed0d5ea Rearrange signed mode for mulhsu 2016-04-13 17:28:37 +02:00
Andreas Traber
cf5815a5e6 Fix a small bug in the short multiplier 2016-04-13 16:10:05 +02:00
Andreas Traber
d521ff3857 Also support mulhsu, so now we have the full set of the M extension 
Currently still deactivated since they clash with p.mac and p.msu, so we
first have to move those away
 2016-04-13 15:16:56 +02:00
Andreas Traber
4cae220197 Add support for mulhu as well 2016-04-13 14:12:53 +02:00
Andreas Traber
5839e120bd Basic mulh implementation in 4 cycles 2016-04-13 12:40:56 +02:00
Andreas Traber
3a96261dac Bit of beautify 2016-04-12 11:11:45 +02:00
Andreas Traber
9278b0ebd0 Silence unique warnings by either adding defaults or removing unique 
where unnecessary
 2016-04-11 16:09:26 +02:00
Andreas Traber
e899af4395 Fix syntax error for RTL compiler 2016-04-06 17:47:29 +02:00
Andreas Traber
98d353806c integrate ext[hb][sz] into shuffle pack data path 2016-04-06 09:32:52 +02:00
Andreas Traber
a6976b443b Add proper targets for sub-ips 2016-04-01 13:41:31 +02:00
Andreas Traber
8edb42244b Fix a compressed instruction decoding error 
If the register 0b01000 was selected for srai and srli for a compressed
instruction, it was considered an illegal instruction which is wrong

This is a legacy from the specification changes from >6 months ago
 2016-04-01 10:58:16 +02:00
Andy Traber
1f2659d380 Linting 2016-03-31 17:33:04 +02:00
Andreas Traber
6ee9f3fe92 Fix wrong ordering of instructions in tracer in some cases 2016-03-31 10:32:19 +02:00
Andreas Traber
c786516d6c Add p.elw to tracer 2016-03-31 09:38:52 +02:00
Andreas Traber
d06042d7b1 Fix some synthesis warnings 2016-03-30 13:27:06 +02:00
Andreas Traber
3859f66a1e Disable simulation checker again.. i should really take care of this 2016-03-24 18:15:33 +01:00
Andreas Traber
68afee79a6 Added support for dot product 2016-03-24 17:55:20 +01:00
Andreas Traber
aa28fac157 Fix a nasty L0 buffer bug that happens with hardware loops 2016-03-24 17:54:55 +01:00
Andreas Traber
1f2eef7606 Disabled simchecker per default again 2016-03-23 13:38:00 +01:00
Andreas Traber
a45273acc6 Added support for p.add[u][R]N 2016-03-23 13:34:00 +01:00
Andreas Traber
8cf1e0e845 Add support for the clip operation 2016-03-17 17:42:11 +01:00
Andreas Traber
99f7a2c50b Shuffle pack seems good after testShufflePack passes 2016-03-17 12:48:57 +01:00
Andreas Traber
b55241e3da Add TB for serial divider 2016-03-16 18:53:21 +01:00
Andreas Traber
b35c431632 Add alu_div also to src_files 2016-03-16 16:33:51 +01:00
Andreas Traber
41dc5f3aa0 New version of divider, variable latency and thus faster on average 2016-03-15 18:13:35 +01:00
Andreas Traber
4401708fdb Add preliminary version of shuffle/pack 
There are still some bugs in it, but the data path is done
 2016-03-15 13:27:12 +01:00
Andreas Traber
d1db668404 Different optimizations in the ALU to make it smaller 
- New generation for ff1, fl1, clb
- Muxing for ff1, fl1, clb is different
 2016-03-11 17:10:57 +01:00
Andreas Traber
28b5a8e8dc Remove final mux for divider (costs one cycle) and always subtract 2016-03-11 13:56:29 +01:00
Andreas Traber
e8cc64fda6 First version of bit-serial divider 2016-03-10 15:45:56 +01:00
Andreas Traber
47b713fd0d Add vector instructions to simulation tracer 2016-03-03 13:34:58 +01:00
Andreas Traber
96e6eb82d9 We should also active the WE for vectorial instructions... 2016-03-03 13:14:39 +01:00
Andreas Traber
7e07801be1 Switch bclr and bset instructions to comply with spec 2016-03-03 10:56:00 +01:00
Andreas Traber
4ff7d58f02 Comment simchecker, should not be enabled per default 2016-03-02 17:04:29 +01:00
Andreas Traber
4e587ececf Make sure that core_busy signal knows about the new data event load 2016-03-02 15:33:46 +01:00
Andreas Traber
217adf9dc0 Add special event load instruction (p.elw) 2016-03-02 14:26:29 +01:00
Andreas Traber
3b127ca326 Added support for pv.insert, pv.extract and pv.extractu 
All untested so far
 2016-03-02 14:04:07 +01:00
Andreas Traber
09d6de8e42 Fixed vector opcode and added vectorial shifts 2016-03-02 13:17:40 +01:00
Andreas Traber
9319fc71c1 Added min/max/abs support 2016-03-02 11:15:32 +01:00
Andreas Traber
06144c2fbe Added partitioned adder for vectorial operations 
This takes care of:
 - pv.add
 - pv.sub
 - pv.avg
 - pv.avgu
 2016-03-02 11:01:35 +01:00
Andreas Traber
3495998840 Added vectorial comparisons and started decoding the rest of the vectorial operations, still needs testing though 2016-03-02 10:11:48 +01:00
Andreas Traber
4efa86705c Added pv.ball instruction 2016-02-25 14:21:50 +01:00