Sven Stucki
3a992372d6
Merge branch 'rvc18'
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Adds support for the updated RVC extension. The spec is not final yet, but the
compiler already supports and uses it. This update makes it possible to use
the most up-to-date compiler version.
2015-09-25 13:19:41 +02:00
Andreas Traber
1aa8b78a73
Prefetcher now tells the core when it is safe to shut down
2015-09-24 16:32:17 +02:00
Andreas Traber
4571bc30ae
Make instr_addr_o in prefetcher independent of instr_rvalid_i
2015-09-24 13:20:11 +02:00
Andreas Traber
efb607a792
Fix exception problem after stages are more independent
2015-09-24 13:16:18 +02:00
Andreas Traber
415546609e
Simplify rdata output from prefetcher, we can simply use the higher part
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of rdata_o for rdata_unaligned_o, it's the same after all, always
2015-09-24 09:59:04 +02:00
Andreas Traber
2f89182e8b
Clear prefetch bit when branch is incoming
2015-09-24 09:32:28 +02:00
Andreas Traber
cc90e85471
Fix RVC handling in prefetch_L0_buffer
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The code is not so nice and should be further cleaned up
2015-09-23 17:25:15 +02:00
Andreas Traber
b41b2a697d
Further cleanups, try to make the code a bit easier to understand...
2015-09-23 17:25:15 +02:00
Flo Zaruba
d988f06f0e
Fixed synopsis syntax error
2015-09-23 15:44:03 +02:00
Andreas Traber
88614ea124
Fix id_valid signal propagation to exception controller
2015-09-23 15:33:02 +02:00
Andreas Traber
a3256c4df2
Fix small error in prefetcher where GNT occur one cycle after we wanted
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to prefetch
2015-09-23 15:32:30 +02:00
Sven Stucki
b5c885b027
Cleanup compressed decoder
2015-09-23 14:12:34 +02:00
Sven Stucki
6ececfc676
Update compressed_decoder to RVC v1.8
2015-09-23 14:11:42 +02:00
Andreas Traber
9ceeb15bc8
This fixes the instruction fetch miss performance counter
2015-09-22 16:35:16 +02:00
Andreas Traber
072cd65e65
Change indentation of prefetch buffer to match RI5CYs style
2015-09-22 12:50:28 +02:00
Andreas Traber
74f5d5c0a4
Integrated prefetch_L0_buffer from Igor
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We can now pass icache lines directly to the core
2015-09-22 11:14:16 +02:00
Andreas Traber
49f7249b0a
Decentralize stall control
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Stall control for IF/ID pipeline is not yet ideal though, we could still
gain one or two cycles there
2015-09-21 18:26:08 +02:00
Andreas Traber
e98e47b9e5
Something went wrong in the cherry-pick, remove remains of timer
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Rename decoder to riscv_decoder to avoid naming conflicts with hwpe
2015-09-18 13:12:56 +02:00
Flo Zaruba
90cc39a9ca
Exception controller update
2015-09-17 13:52:11 +02:00
Flo Zaruba
d274068643
Cherry pick 1
2015-09-17 13:51:54 +02:00
Andreas Traber
8fe67b303d
Run through linter and do some cleanup
2015-09-15 13:08:26 +02:00
Andreas Traber
9858caff47
Separated decoder and controller and cleanup
2015-09-15 12:52:15 +02:00
Andreas Traber
d27a2a3f63
Various debug related improvements
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Implemented c.ebreak instruction
Debugging with rvc seems to work properly now
2015-09-15 09:46:04 +02:00
Andreas Traber
10ae9df25a
Remove movhi ALU opcode, it is of no use for RI5CY
2015-09-14 15:53:17 +02:00
Andreas Traber
d2a549bfae
Fix misaligned access, they did not correctly forward and used the wrong
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increment...
2015-09-14 12:46:46 +02:00
Andreas Traber
1b2a80e7c9
Oops... is_compressed can of course no longer be generated in id stage
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but must be pipelined from if stage
2015-09-11 17:42:15 +02:00
Andreas Traber
52d3608a93
Simplify exception controller and make sure external IRQs work as well
2015-09-11 14:06:38 +02:00
Andreas Traber
0608b98440
Make illegal instruction exceptions work again
2015-09-11 13:14:56 +02:00
Andreas Traber
e41c7b96be
Change LSU to use correct protocol
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With prefetching there is no long path to the icache anymore starting
from the LSU, so this modification is no longer critical
2015-09-10 13:12:19 +02:00
Andreas Traber
6fb05eab34
Rename instr_core_intf to prefetch_buffer, add if_busy signal again
2015-09-10 13:12:19 +02:00
Andreas Traber
84ea2c90ee
Fix aborting on instr core interface
2015-09-10 13:12:19 +02:00
Andreas Traber
463e74cf05
Only stall IF fsms when absolutely necessary
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This should take care of our synthesis issues (hopefully)
2015-09-10 13:12:19 +02:00
Andreas Traber
847b652ce5
Change IF fifo depth to 3 to get performance from old IF back
2015-09-10 13:12:19 +02:00
Andreas Traber
db82a7ab8e
Fix problem with unaligned compressed access
2015-09-10 13:12:19 +02:00
Andreas Traber
e0ea57968b
Prefetcher basically done, works in pulpino without rvc
2015-09-10 13:12:19 +02:00
Andreas Traber
79bce5b31b
Add a basic datasheet for RI5CY
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Not very detailed yet, needs a lot of work still
2015-09-09 18:35:07 +02:00
Andreas Traber
b347299f31
Move compressed decoder/expander to IF stage
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I.e. the decoder is now before the IF/ID pipeline
It turns out there is enough timing budget to put it there and thus it
simplifies timing in the ID stage
2015-09-08 19:33:10 +02:00
Sven Stucki
f5e1020f57
Add performance counter for compressed instructions
2015-09-08 17:24:39 +02:00
Andreas Traber
a330a8fe70
Improve inline comments in if_stage
2015-09-07 16:02:32 +02:00
Sven Stucki
216362365c
Fix hwloop we
2015-09-07 11:53:21 +02:00
Sven Stucki
c2b519786b
Merge branch 'hwloops'
2015-09-07 03:41:28 +02:00
Sven Stucki
b5aea15659
Finish hwloops addition
2015-09-07 03:40:28 +02:00
Sven Stucki
82afb4c839
Remove another unnecessary signal
2015-09-05 18:15:18 +02:00
Sven Stucki
24f0a588f5
More cleanup, remove unused signal
2015-09-05 16:33:51 +02:00
Sven Stucki
f9d0911329
Cleanup ID
2015-09-05 16:00:41 +02:00
Sven Stucki
a6dc8271e9
Wire up hwloops correctly, other small fixes
2015-09-05 03:37:50 +02:00
Andreas Traber
4f06b67e65
Simplify instr core interface
2015-09-04 15:52:35 +02:00
Andreas Traber
adb40aef43
Make instr_req_o signal dependent only on state
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=> removes ~1 gate from critical path and simplifies paths through i$
This will cost one cycle when waking up from sleep though :-/
2015-09-04 13:54:19 +02:00
Sven Stucki
87e2eec128
Move hwloop regs into ID stage, WIP
2015-09-03 13:39:11 +02:00
Sven Stucki
77ef44a82f
Separate jump target calculation from jump_in_id
2015-09-03 02:08:48 +02:00
