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6031 commits 5 branches 76 tags 278 MiB
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69 commits

Author SHA1 Message Date
stnolting
7e7e360b7f ⚠️ [top] remove fence signals 2024-02-09 16:58:30 +01:00
stnolting
8cfb56f286 [top] update/add XIP generics 2024-02-09 11:50:39 +01:00
Unai Sainz-Estebanez
8211c76948 Fix-up the litex wrapper 2023-11-07 12:24:59 +01:00
stnolting
31a541ed22 [rtl] remove Zifencei generic 2023-10-18 21:49:30 +02:00
stnolting
83cd3109f9 [litex] comment fix 2023-09-21 21:34:15 +02:00
stnolting
8c90c81388 [AXI wrapper] connect external MTIME IRQ 2023-09-15 20:37:36 +02:00
stnolting
abe9424331 [rtl] typo fixes 2023-09-11 21:28:16 +02:00
stnolting
bf5c66a6e3 [AXI wrapper] update; add missing generics and signals 2023-09-11 21:17:40 +02:00
stnolting
bfaeb5fc6d [rtl] fix 2023-07-29 12:51:26 +02:00
stnolting
7a4b45e680 remove CPU_IPB_ENTRIES generic 2023-07-29 11:31:06 +02:00
stnolting
9b386cc2ae ⚠️ remove CUSTOM_ID generic 2023-07-27 09:52:26 +02:00
stnolting
70d5f6b0da [rtl wrappers] remove Zicsr generic 2023-03-29 21:01:16 +02:00
stnolting
a4efa1409b [rtl] fix litex wrapper - take two 2023-03-25 14:46:36 +01:00
stnolting
d00ce96859 [rtl] fix litex wrapper 2023-03-25 14:43:18 +01:00
stnolting
495639a663 [rtl/system_integration] add d-cache generics 2023-03-25 14:32:34 +01:00
stnolting
4c65442074 [rtl/system_integration] generic cleanups 2023-03-18 16:04:21 +01:00
stnolting
e69b598a21 [rtl/system_integration] fix entity signal types; remove default values 
std_ulogic -> std_logic
 2023-03-16 20:08:51 +01:00
stnolting
2c25612175 move tri-state drivers out of core 
ONEWIRE and TWI
 2023-03-09 19:47:27 +01:00
stnolting
cf327e7489 re-add RTS/CTS top signals 2023-03-08 19:20:02 +01:00
stnolting
a4e11fd5f7 UART: remove RTS/CTS ports 2023-03-05 18:36:23 +01:00
stnolting
00a0c96caa update SPI FIFO generic constraints 2023-03-04 11:38:33 +01:00
stnolting
49f4f7e53c [rtl]system_integration] another typo fix... 2023-02-24 17:31:49 +01:00
stnolting
956ee325e7 [rtl/system_integration] typo fixes 2023-02-24 17:28:23 +01:00
stnolting
15328dd417 ⚠️ rename SPI & XIP top ports 2023-02-24 17:22:10 +01:00
stnolting
65ac9633bd ⚠️ [rtl] remove SLINK interface module 2023-02-22 20:51:37 +01:00
stnolting
821a5a2f37 update PWM generic and port 2023-02-19 18:14:28 +01:00
stnolting
74cc86ad3d [rtl] remove std_logic wrapper 2023-02-11 19:08:20 +01:00
stnolting
4dc1b166d4 [rtl, sim] update GPIO generic 2023-02-11 19:08:07 +01:00
stnolting
8e9286a217 [rtlsystem_integration] remove mtime ports 2023-01-15 10:25:01 +01:00
stnolting
8759c0d3a6 [rtl] update IPB configuration generic 2022-12-13 18:55:25 +01:00
Florent Kermarrec
e269f08419 litex_core_complex: Expose configuration constants as generics. 
The VHDL -> Verilog conversion flow can now configure the generics before
the conversion. This avoid the workaround that was modifying the constants
in litex_core_complex during the build.

Corresponding LiteX's PR: https://github.com/enjoy-digital/litex/pull/1460.
 2022-10-12 14:56:31 +02:00
stnolting
0913507abe [rtl/system_integration] remove CPU_CNT_WIDTH generic 2022-09-08 20:32:51 +02:00
stnolting
fda384f0c6 [rtl/system_integration] add ONEWIRE generic and port 2022-09-01 14:35:41 +02:00
stnolting
c71dd090f7 [system_integration] add SPI FIFO generic 2022-07-31 19:26:29 +02:00
stnolting
c8ddb6a632 [rtl] add CUSTOM_ID generic 
Can be used to set a user-defined identifier or to pass user-defined config flags. Can be retrived by SW from the SYSINFO memory.
 2022-07-22 15:06:59 +02:00
stnolting
722ab46f0a [rtl] fix IPB size 
when having a (large) cache a large instruction prefetch buffer is not needed at all
 2022-07-19 12:58:17 +02:00
stnolting
e15ea70e8c [LiteX] replace generics by constants 
#350
 2022-07-05 20:24:43 +02:00
stnolting
a9d4b055a8 [LiteX] change "standard" cache layout 
#350
 2022-07-01 10:18:33 +02:00
stnolting
d2789f3b43 minor comment edits 2022-06-29 13:26:23 +02:00
stnolting
3f2f42b576 minor comment edits 2022-06-28 21:30:50 +02:00
stnolting
c68059a369 remove Wishbone tag signal 2022-06-28 17:54:32 +02:00
stnolting
79210d809e remove fence signals 2022-06-28 17:52:39 +02:00
stnolting
ad844a2837 [rtl/system_integration] add LiteX core complex wrapper 2022-06-24 20:30:54 +02:00
stnolting
407fdbbc52 [rtl/system_integration] add wishbone async TX generic 2022-06-20 18:05:26 +02:00
stnolting
f5d3e610f9 [rtl] wrappers: add SLINK LAST signals 2022-06-16 12:36:34 +02:00
stnolting
45697c3c72 🐛 default value "bug"/typo fix 2022-05-20 15:31:36 +02:00
stnolting
fdbd3cd61d add IO_TRNG_FIFO generic to wrappers 2022-05-17 16:34:57 +02:00
stnolting
4e73f3edfd rtl fix 2022-04-27 12:03:30 +02:00
stnolting
e080af088e remove A extension from wrappers 2022-04-27 11:58:20 +02:00
stnolting
099fe4e08e limited max PMP regions to 16 entries 2022-02-27 13:26:54 +01:00