- Fix the AXI ID width for the CLINT (previously `4`, now `5`)
- Parametrise the CLINT's AXI types
- Deprecate `axi_[master|slave]_connect` and move to AXI assign macros,
as they allow arbitrary AXI types
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
* Change questa version reference format
* bump common_cells to v1.23
* Bump axi to v0.31.0, replace axi_node with axi_xbar
* Bump register_interface for axi compatibility
* add prot signals to axi_lite for compatibility
The performance counters were accessible in user mode although
`mcounteren` or `scounteren` are not implemented. This commit moves the
writeable performance counters to machine mode. Access from
user/supervisor-space will trap as this is not implemented in Ariane.
When speculation is on it can happen that the core is trying to fetch
from a wrong, speculated address. Depending on the SoC this can cause
lock-ups. Solution until now was to flush all branchprediction which is
quite costly in terms of performance. This commit fixes this and lets
the `frontend` check whether the access is actually legal.
This make execution more deterministic as we can decide early
whether the remaining pipeline is speculative or not. Furthermore it
removes a couple of logic gates during commit and clean-s up the tight
integration between `commit_stage` and `csr_regfile` which often lead
to combinational loops.
This patch is in preparation to fixing speculative reads to I/O regions.
Upon start the `debug_req` signal is being delayed for a couple of
cycles to give the core enough time to initialize `a0` and `a1` with its
`hartid` and a pointer to the `dts` (e.g. executing the first
instructions of the ZSBL). This fixes issue #211.
Use a PLIC which has been developed as part of the lowrisc project. It
has been integrated into the Ariane SoC as a submodule pointing to a
fork which has some (temporary) custom patches on top.
* Add spike isa sim
* Fix AMO problem in verilator
* 🎨 Tidy up FPU wrapper
* Bump axi_exclusive submodule
* Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190)
* Refactor serpent AXI adapter
* Disable FPU in OpenPiton by default
* Bump dbg and atomics submodules
* Fix cache testbenches (interface change)
* FPGA bootrom changes for OpenPiton SDHC
* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD
* Testing barrier-based synchronisation instead of CLINT-based
* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707
* Add MAX_HARTS switch to makefile
* Fix gitlab CI
* Revert standard FPGA bootrom
* Update Flist
* Make UART_FREQ a parameter
* Fix typo in tb.list and an error in define switch in ariane_pkg
* Copy over SD-driver in bootloader from @leon575777642
* Fix compilation issues of bootrom
* Change signal name in serpent periph portlist
* Correct generate statement in serpent dcache memory
* Add Piton SD Controller, FPGA fixes
* Fix race condition in dcache misshandler
* Add tandem spike to Make flow
* Remove OpenPiton SD Card controller again
* : Fix PITON_ARIANE define issues
* Fix write-back / cache read collision issue in serpent dcache.
* Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment).
* Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane.
* Fix assertion in icache.
* Correct JTAG timing constraints.
* Fix parameter type in fpga toplevel (fix#168).
* Remove conflicting bootrom from fpga file list.
* This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs).
* Fix byte offset of IPIs in CLINT
* Disable DCache flushes on fence for write-through cache (not needed in that case)
* Fix blocking assignments in ff process.
* Fix register access issue in debug mode, only affects A0 (fix#179).
* Fix multiple driver issue in PLIC
* Do not assume replicated data in serpent dcache when reading from an NC region.
* Another byte offset fix in IPIs (CLINT)
* Add AXI64 compliance switch to dcache_mem
* Fix genesys 2 constraints
* Map serpent atomic requests onto AXI atomic/exclusive transactions.
* Cleanup of AXI memory plumbing, add separate AXI adapter module.
* Remove unneeded interface signals, increase wbuffer #pending tx
* Fix verilator compilation issues in AXI adapter.
* Delete unnecessary constraint
* Delete duplicate module instance
* Update gitlab CI script
* Small fixes to make riscv atomics work with serpent_axi_adapter.
* Update travis and gitlab-ci scripts
* Register b responses for better timing.
* Remove fpu div submodule, update Makefile paths and src lists
* Constant bits in haltsum reduction must be 1 (AND reduction).
* Switch to DTM from riscv-dbg submodule
* Further cleanup fixes in AXI/serpent atomics
* Bump riscv-dbg version
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
* Fix latch and timing loop in debu_req
* Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE
* Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data
* Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode.
* Initialize instruction traced shadow regfile to zero at start of simulation
Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X
Fix printouts of assertions
Modify bootrom to prevent assignment of X to output
* Make separate CI target for AMO tests
* Bump fpga-support version
* Add AMO tests list
* Fix FPU submodule version
* Change core_id + cluster_id into hart_id
* Rename gitlab CI tests
* Replace all SYNTHESIS macros with pragma translate_off
* Update readme, bump common cells, benderize
* Fix torture make target
* Remove unneeded signal
