Usage of the macros:
* If defined, VM_TRACE enables tracing. If macro VM_TRACE_FST is not defined (the default), waveform generation will use VCD format. If the command-line option -v FILE or --vcd=FILE is given to the compiled simulator, the VCD output will be written to file named FILE in the current working dir of the verilated simulator. If no -v/--vcd= option is given on cmdline, or an FST-specific trace option is used, the simulator will generate a VCD trace according to the settings in the RTL code.
* if VM_TRACE_FST is defined as well, then FST format is used instead of VCD. If the command line option -f FILE or --fst=FILE is given to the simulator, the trace will be stored in file FILE in the current working dir of the verilated simulator. If no -f/--fst= option is given, or a VCD-specific trace option is used, the simulator will generate an FST trace according to the settings in the RTL code.
* wb_dcache: Forward "atomic transactions" to AXI
* Correct bugs
* Forward LR/SC atomics
* Fix CI
* miss_handler: Route AMO port through arbiter
* axi_adapter: Correct LOAD AMOs handling
Accept read data only after (or together) handshake on B channel
* Restore old ID
* Correct atop encodings
* Correct AMOs AXI ID
* Correct wb_dcache testbench
Previously not comparing AMOs at all! Due to amo_exp_resp being 'x
* Realign and sign extend 32b request rdata
* Use axi_pkg definitions for ATOPs encoding
* Remove whitespace
* wb_dcache: Style corrections
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
- Fix the AXI ID width for the CLINT (previously `4`, now `5`)
- Parametrise the CLINT's AXI types
- Deprecate `axi_[master|slave]_connect` and move to AXI assign macros,
as they allow arbitrary AXI types
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
* Change questa version reference format
* bump common_cells to v1.23
* Bump axi to v0.31.0, replace axi_node with axi_xbar
* Bump register_interface for axi compatibility
* add prot signals to axi_lite for compatibility
* Add top hierarchy modification and rs3 for general purpose register file
* CVA6 core modifications to enable CoreV-eXtension-Interface feature
* Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6
* CoreV-eXtension-Interface available for FPGA
* Add work directories to gitignore
* Flist: fix cvxif files
* CVXIF: Modification and bugfix for cvxif feature
* CVXIF: simplify destination register feature
* Make 3rd read port on regfile configurable
* example_copro: use fifo_v3 instead of stream_fifo
* Makefile: compilation copro using defines
* ariane_pkg,riscv_pkg: add parameter to en/disable cvxif
* cva6.sv, ariane.sv: add hierarchy between ariane and cva6
* Clean Up code and typo
* CVXIF: moved combinatorial part to cvxif_fu module in ex_stage
* instr_decoder: rename instr predecoder and package
* Clean Up code and typo
* cvxif modification to follow style guideline
* issue_read_operands.sv: fix always_ff block for cvxif functionnal uni
* Makefile: Implement the plateforms defined in cva6 specification
target variable can take cv64a6_imacfd_sv39, cv32a6_imac_sv0,
cv32a6_imac_sv32, cv32a6_imacf_sv32
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix plateform name: from imacfd to imafdc
from imacf to imafc
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Fix the VCS flow for 64-bit CVA6 by only adding compatible MMU
sources. For instance, `mmu_sv32` assumes `PLEN` > `VLEN`, which
is not the case for RV64.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
*_slv_t types are needed only in ariane_testharness.
The CVA6 core should not depend on packages related to the SoC
where it is placed.
Signed-off-by: Luca Zulberti <zulberti.luca@gmail.com>
* Fixed multithreading and optimization options for verilator Makefile target
Signed-off-by: Shengjie Xu <shengjie.xu@mail.utoronto.ca>
* Dropped the -j option in the make commands of Travis CI's verilator tests
Signed-off-by: Shengjie Xu <shengjie.xu@mail.utoronto.ca>
* Limit the optimization flag to verilator target
Signed-off-by: Shengjie Xu <shengjie.xu@mail.utoronto.ca>
* Moved -O3 to CFLAGS from verilator-only flags
Signed-off-by: Shengjie Xu <shengjie.xu@mail.utoronto.ca>
The tests have been spread to many smaller tests previously to avoid CI timeouts.
With memory preloading the overhead of setting up the tests is dominating so we
merge the tests again.
Also remove `rv64ui-v-fence_i` from test list as it is currently failing.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
Pre-load the Verilator memories through a side-band signal. We have sub-classed
the dtm_t module to prevent the debugger from pre-loading. This commit also
updates the stale bootrom.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
Add a register file, optimized for synthesis on FPGAs supporting
distributed RAM.
Principle:
The baseline implementation implements the register file as an array of
flip-flops and implements large multiplexers for read- and write-
accesses. On FPGAs, we have a more efficient implementation for data
storage: By using distributed RAM for memory storage, we can store up
to 64 bits in just one LUT (depending on the memory layout and FPGA
device). In addition, distributed RAM comes with integrated address
decoders. The register file features one distributed RAM block per
implemented sync write port, each with the parametrized number of
async read ports. The read access is arbitrated depending on which
block was last written to. For this purpose an additional array of
*NUM_WORDS* registers is maintained keeping track of write accesses.
Since both FFs and multiplexers are an expensive structure on FPGA
technology, the achieved savings are considerable. The register file
is used for the FPU and general purpose register files.
Concrete Savings: (Xilinx Kintex-7, xc7k325tffg900-2)
```
LUT FF LUTRAM
---------------------------------
baseline: 40499 22799 0
optimized: 36350 18806 440
---------------------------------
Diff -4149 -3993 +440
-10.2% -17.5%
```
Signed-off-by: ganoam <gnoam@live.com>
* Summary: initial dromajo integration
* some changes to Makefile to enable `make verilate DROMAJO=1`
* adding ifdefs to ariane_tb.cpp to disable HTIF
* adding dromajo repo
* making dromajo repo a submodule
* syncing with upstream
* bumping to the latest dromajo commit
* Summary: adding DPI functions for cosim
* added new file tb/dpi/dromajo_cosim.cc that contains
all DPIs for dromajo to work
* editted Makefile to see the above file
* Summary: fixing build issues
* fixing syntax errors in dpi file
* renaming dpi file due to name conflict with shared library
* fixing path in Makefile to the shared dromajo lib
* bumping to the latest dromajo change
* Summary: loading checkpoint to bootrom
This change adds `+checkpoint=` argument to the verilator simulator
as well as corresponding changes to load the dromajo checkpoint into
the bootrom. Dromajo checkpoint bootcode contains series of csrw and
immediate loads to restore the architectural state of the processor.
dromajo_bootrom.sv
is a copy of a generated bootrom.sv file. This
file parses the verilog plusargs and loads the bootrom with the code
that is pointed by the +checkpoint.
csr_regfile.sv
Dromajo needs to start running the code in debug mode. The default
value of debug_mode_q was changed to 1.
* updating dromajo to the latest change
* Summary: sync main memories of dromajo and ariane
These changes load the checkpoint into the main memory of Ariane.
The checkpointed memory that is dumped from dromajo contains
(1) the binary and (2) the values of all stores that dromajo
globally performed before dumping the checkpoint.
dromajo_ram.sv
This file is a copy of SyncSpRamBeNx64.sv and was modified to parse
+checkpoint argument to load the memory from the path pointed by
the argument.
The remaining changes were introduced to instantiate the above file
when DROMAJO=1 flag is set.
* Summary: calling DPIs for cosimulation
This change introduces the calls to DPI functions that interface
with Dromajo.
* updating to the latest commit of dromajo
* disabling verbose output when preloading bootrom and mainram
* Summary: bug fix - update logic of `dcsr_d.prv`
This change was made per discussion with Florian via email. The
current versionincorrectly implements the update logic of
`dcsr_d.prv`.
The confusion came from the fact that the core should update its
`dcsr_d.prv` to the current running privilege level when entering
debug mode. I've attached a patch which, as you suggested, removes
the wrong update logic in the CSR write process and should now
correctly handle the update when entering debug mode
(4.9.1 Debug Control and Status of the debug specification).
* bump to the latest version of dromajo
* Summary: dromajo DPI change
This change:
* Ariane doesn't commit ebreaks and ecalls so some workaround
was encorporated
* Proper exit(0) on cosim pass
* Summary: support for running binaries with dromajo
This change adds the ability to run the following command:
`make run_dromajo BIN=\path\to\riscv\bin`
It automates the dromajo's checkpoint creation and runs the binary
on Ariane with dromajo cosimulation.
For this to work Ariane must be build with DROMAJO=1.
* changing dromajo recipe name to be consistent with existing names
* adding instructions on how to run cosim with dromajo
* Bump to release 0.6.2
* added license headers
* added more details about dromajo
