Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap
Add the HPDcache as another alternative for the cache subsystem.
The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
`elf-bin` is propagated to fesvr via the plusplus arg. Since #1240, running
```
make sim elf-bin=path/to/elf
```
returns
```
terminate called after throwing an instance of 'std::runtime_error'
what(): could not open
+PRELOAD=path/to/elf (did
you misspell it? If VCS, did you forget +permissive/+permissive-off?)
```
As per the README, if preloading is needed, `make sim preload=path/to/elf` should be used
instead (https://github.com/openhwgroup/cva6/tree/master#memory-preloading),
which sets `+PRELOAD=path/to/elf`
(6c89fda0da/Makefile (L249-L253)).
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
* Makefile (CFLAGS): Use C++ 2017 standard. Fix whitespace.
(src): Fix whitespace.
($(dpi-library)/%.o): Do not add another (potentially conflicting) C++
standard option.
* ariane.core (verilator_options): Use C++ 2017 standard.
Propagate the CFLAGS specified in the environment executing
the Makefile for DPI compilation. The current CFLAGS are
extended by the CFLAGS from the environment.
