JeanRochCoulon
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184ccc0e58
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Add Verible command to the CONTRIBUTING.md file (#2067)
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2024-04-22 17:21:44 +02:00 |
|
JeanRochCoulon
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e1d61182b7
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Generate the cv32a65x riscv specification out of the box (#2054)
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2024-04-22 15:34:21 +02:00 |
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MarioOpenHWGroup
|
8a9d7a832b
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Fix RVFI always_ff blocks (#2053)
|
2024-04-18 10:06:34 +02:00 |
|
Florian Zaruba
|
377b0de154
|
Fix SuperScalar config and add CVA6Cfg to first pass decoder (#2047)
* Add `CVA6Cfg` to first pass decoder
* Fix `verilator` `SELRANGE` warnings
* Update core/decoder.sv
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
* Update core/cva6_accel_first_pass_decoder_stub.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/decoder.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/frontend/instr_queue.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
---------
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
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2024-04-17 16:34:08 +02:00 |
|
CoralieAllioux
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82b2d15127
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Add ifdef for VCS fix (UNSUPPORTED_WITH) (#2041)
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2024-04-17 15:56:52 +02:00 |
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JeanRochCoulon
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9a36bf2c3d
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define riscv-isa-manual as submodule (#2052)
* remove riscv-isa-manual vendor
* Define riscv-isa-manual as submodule
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2024-04-17 12:45:43 +00:00 |
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Nils Wistoff
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e84b271cff
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ci/hyp: Fix reference to riscv-hyp-tests (#2051)
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2024-04-17 14:01:35 +02:00 |
|
Juan Granja
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2182aee119
|
Update ariane_xilinx.sv (#1954)
|
2024-04-17 11:18:20 +02:00 |
|
Zbigniew Chamski
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c51fad1d0e
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Vendorize 'riscv-config' tool in order to test/support local extensions. (#2045)
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2024-04-16 13:56:06 +02:00 |
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dependabot[bot]
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75f695f665
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Bump verif/core-v-verif from 4f9dd2a to f7bda8e (#2043)
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2024-04-15 22:23:15 +02:00 |
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CoralieAllioux
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fb43d778b3
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[UVM] Few LRM compliance fixes (#2042)
|
2024-04-15 16:44:34 +02:00 |
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MarioOpenHWGroup
|
71ef48804a
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[RVFI] Optimize CSRs (#1999)
|
2024-04-15 16:29:07 +02:00 |
|
JeanRochCoulon
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e1ee77e02d
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define WtDcacheWbufDepth as cva6 parameter and fix rvfi.svh (#2040)
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2024-04-15 15:05:30 +02:00 |
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Zbigniew Chamski
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e2401d3e88
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[HOTFIX] Add missing 'build' directory belonging in vendorized ISA docs. (#2039)
|
2024-04-15 13:07:30 +02:00 |
|
André Sintzoff
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1e93175dd4
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testlists for cv32a65x: add files (#2037)
|
2024-04-12 17:47:03 +02:00 |
|
Moritz Schneider
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0a160c9294
|
Fix reserved value in MPP (#2035)
|
2024-04-12 11:13:17 +02:00 |
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JeanRochCoulon
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5df5a5c247
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Define InstrTlbEntries, DataTlbEntries, cfg.NrLoadPipeRegs, NrStorePipeRegs, DcacheIdWidth as CVA6 parameters (#2034)
|
2024-04-12 09:06:35 +02:00 |
|
André Sintzoff
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9bd5667992
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decoder.sv: fix ZEXT.H instruction (fix #1758, #1975, #2010) (#2032)
- add missing ZEXT.H for RV64
- fix ZEXT.H for RV32: bit[24:20] shall be 0
|
2024-04-11 16:38:11 +02:00 |
|
JeanRochCoulon
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527a989542
|
Clean-up 65x config_pkg.sv file by removing the localparams (#2031)
|
2024-04-11 11:29:31 +02:00 |
|
Côme
|
d6c37051c3
|
fix util/user_config.py for DCacheType (#2028)
|
2024-04-10 23:53:07 +02:00 |
|
Florian Zaruba
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ecd6ed6b6b
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Move DCacheType to config struct (#2025)
|
2024-04-10 23:26:21 +02:00 |
|
Jalali
|
bfff84eaeb
|
Fix issue #2018 (#2023)
|
2024-04-09 17:43:21 +02:00 |
|
Moritz Schneider
|
fa2cea2d65
|
Fix PMPCFG WARL behavior (#2019)
|
2024-04-09 16:40:00 +02:00 |
|
Côme
|
1c529d68ce
|
superscalar: return 2 instructions from instruction queue (#2022)
|
2024-04-09 16:39:24 +02:00 |
|
Côme
|
512296b9be
|
ci: perform synthesis on cv32a6_embedded only (#2021)
|
2024-04-09 11:17:44 +02:00 |
|
JeanRochCoulon
|
f4ec364bf4
|
Fix MIE CSR described in #2004 and #2008 Github issue (#2017)
|
2024-04-08 19:54:55 +02:00 |
|
Moritz Schneider
|
90d780eb14
|
Fix PMP CSR locked behavior (#2015)
|
2024-04-08 14:01:14 +02:00 |
|
valentinThomazic
|
4f73867fce
|
Do not add spike param arg if no spike param provided (#2016)
|
2024-04-08 12:03:20 +02:00 |
|
JeanRochCoulon
|
80e6d7cffc
|
Verible reformat (#2014)
|
2024-04-08 11:26:08 +02:00 |
|
Côme
|
ec44b22920
|
superscalar: fetch 64 bits (#2013)
|
2024-04-08 11:25:39 +02:00 |
|
JeanRochCoulon
|
c6f81d74c4
|
Remove parametrization Warning in README.md (#2011)
As th ebig change due to parametrization is over, I propose to remove the warning.
|
2024-04-08 10:33:28 +02:00 |
|
Cesar Fuguet
|
83a5b05752
|
hpdcache: update submodule (#2009)
|
2024-04-05 18:52:10 +02:00 |
|
Zbigniew Chamski
|
a6fc375dc6
|
[DVplans] Fix broken paths to VPTOOL. (#2007)
|
2024-04-05 18:21:39 +02:00 |
|
Florian Zaruba
|
38e8c059b2
|
Parameterization and other fixes for downstream project (#1950)
* Bender fixes and switch to `cva6_fifo_v3`
* cfg: Fix verilator warnings
* Bender: Fix yml
* acc_dispatcher: Add `csr_addr_i`
* parameterization: Fox AXI_USER_EN warning
* wb_cache: Fix Verilator Lint warnings
* cva6_fifo_v3: Add to Flist
* parameterization: Address review concerns
* Switch to `cva6_fifo_v3`
* tracer: Remove tracer interface
The interface made a bunch of problems with the
typedefs so I've removed it.
---------
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
|
2024-04-05 13:02:18 +02:00 |
|
Côme
|
f886713754
|
User config generator becomes a Python tool to work with configs (#2003)
|
2024-04-04 15:56:29 +02:00 |
|
Saute0212
|
5920e3d125
|
Add support for Nexys Video board (#1925)
|
2024-04-04 11:13:32 +02:00 |
|
valentinThomazic
|
5c7ddcbcc5
|
Fix log naming and dashboard improvements (#2001)
|
2024-04-03 18:03:47 +02:00 |
|
Zbigniew Chamski
|
73e181cdef
|
[Vendorized spec] Add ASCIIdoc inline anchors matching impl-def@1853796c. (#2002)
|
2024-04-03 18:03:33 +02:00 |
|
JeanRochCoulon
|
5fcc71b9d6
|
[HOT FIX] Use cva6_embedded for gate simulation (#1998)
|
2024-04-02 17:56:50 +02:00 |
|
JeanRochCoulon
|
4423feb06a
|
Rename ZiCondExtEn and FPGA_EN parameters (#1992)
|
2024-04-02 15:37:58 +02:00 |
|
dependabot[bot]
|
b401ab3868
|
Bump verif/core-v-verif from 64f8dc1 to 4f9dd2a (#1994)
|
2024-04-02 14:51:58 +02:00 |
|
valentinThomazic
|
3dc1f23a9d
|
Support Spike Parameters in cva6.py and bump core-v-verif (#1976)
|
2024-04-02 10:26:25 +02:00 |
|
dependabot[bot]
|
bcecaf1bdf
|
Bump verif/core-v-verif from 3630a6c to 54c6474 (#1990)
|
2024-04-01 22:41:57 +02:00 |
|
Jalali
|
ea2ccffa78
|
Functional coverage : no need for cvxif directed tests (#1969)
|
2024-03-29 15:41:13 +01:00 |
|
Guillaume Chauvon
|
f884347db4
|
Add debug_disable=1 to match default configuration of cva6.py (#1977)
|
2024-03-29 14:44:03 +01:00 |
|
JeanRochCoulon
|
8d6c1f709f
|
Modify the variable order inside the cva6_user_cfg_t (#1971)
Modify the variable order inside the cva6_user_cfg_t to gather extension params together and micro-architecture params together
|
2024-03-28 15:19:49 +01:00 |
|
dependabot[bot]
|
fbca195283
|
Bump verif/core-v-verif from 004b849 to 3630a6c (#1970)
|
2024-03-28 12:58:35 +01:00 |
|
JeanRochCoulon
|
64273ca4af
|
update Design Doc after bumping H extension (#1968)
|
2024-03-28 09:32:59 +01:00 |
|
Zbigniew Chamski
|
f73724b7e2
|
Vendorize RISC-V specs at tag 2023-10-02. (#1963)
* vendor/riscv/riscv-isa-manual: New vendorized repo.
* vendor/riscv_riscv-isa-manual.lock.hjson: Ditto.
* vendor/riscv_riscv-isa-manual.vendor.hjson: Ditto.
|
2024-03-25 17:52:43 +01:00 |
|
MarioOpenHWGroup
|
08d098bf51
|
[RVFI] Change CSR implementation (#1952)
|
2024-03-25 12:15:18 +01:00 |
|