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João Vitor Rafael Chrisóstomo 2019-09-11 21:17:07 -03:00
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
port (
input_0, input_1 : in std_logic_vector(31 downto 0);
operation : in std_logic_vector(3 downto 0);
branch : in std_logic;
ALU_branch_control : in std_logic_vector(2 downto 0);
ALU_branch_response : out std_logic;
ALU_output : out std_logic_vector(31 downto 0)
);
end entity ALU;
architecture Behavioral of ALU is
signal result_temp : std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
process (input_0, input_1, operation, result_temp, branch, ALU_branch_control) is
begin
result_temp <= "000000000000000000000000000000000";
if (branch = '1') then
case ALU_branch_control is
when "000" => --BEQ (branch if equal)
result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
if (result_temp = "000000000000000000000000000000000") then
ALU_branch_response <= '1';
else
ALU_branch_response <= '0';
end if;
when "001" => --BNE (branch not equal)
result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
if (result_temp = "000000000000000000000000000000000") then
ALU_branch_response <= '0';
else
ALU_branch_response <= '1';
end if;
when "100" => --BLT (branch less than)
result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
if (result_temp(32) = '1') then
ALU_branch_response <= '1';
else
ALU_branch_response <= '0';
end if;
when "101" => --BGE (branch greater than equal)
result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
if (result_temp(32) = '0') then
ALU_branch_response <= '1';
else
ALU_branch_response <= '0';
end if;
when "110" => --BLTU (branch less than unsigned)
result_temp <= std_logic_vector(unsigned('0' & input_0) - unsigned('0' & input_1));
if (result_temp(32) = '1') then
ALU_branch_response <= '1';
else
ALU_branch_response <= '0';
end if;
when "111" => --BGEU (branch greater than equal unsigned)
result_temp <= std_logic_vector(unsigned('0' & input_0) - unsigned('0' & input_1));
if (result_temp(32) = '0') then
ALU_branch_response <= '1';
else
ALU_branch_response <= '0';
end if;
when others =>
ALU_branch_response <= '0';
end case;
else
ALU_branch_response <= '0';
case operation is
when "0000" => -- ALU_output = input_0 + input_1
result_temp <= std_logic_vector(signed(input_0(31) & input_0) + signed(input_1(31) & input_1));
ALU_output <= result_temp(31 downto 0);
when "1000" => -- ALU_output = input_0 - input_1
result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
ALU_output <= result_temp(31 downto 0);
when "0001" => -- shift left logical
ALU_output <= std_logic_vector(shift_left(unsigned(input_0), to_integer(unsigned(input_1))));
when "0010" => -- set less than (signed)
result_temp <= std_logic_vector(signed(input_0(31) & input_0) - signed(input_1(31) & input_1));
if (result_temp(32) = '1') then
ALU_output <= X"00000001";
else
ALU_output <= X"00000000";
end if;
when "0011" => -- set less than unsigned
result_temp <= std_logic_vector(unsigned('0' & input_0) - unsigned('0' & input_1));
if (result_temp(32) = '1') then
ALU_output <= X"00000001";
else
ALU_output <= X"00000000";
end if;
when "0100" => -- xor port
ALU_output <= input_0 xor input_1;
when "0101" => -- shift right logical
ALU_output <= std_logic_vector(shift_right(unsigned(input_0), to_integer(unsigned(input_1))));
when "1101" => --shift right arithmetic
ALU_output <= std_logic_vector(shift_right(signed(input_0), to_integer(unsigned(input_1))));
when "0110" => -- or port
ALU_output <= input_0 or input_1;
when "0111" => -- and port
ALU_output <= input_0 and input_1;
when others => --apenas zera tudo
result_temp(32 downto 0) <= "000000000000000000000000000000000";
ALU_output <= result_temp(31 downto 0);
end case;
end if;
end process;
end architecture Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity EX_MEM_DIV is
port (
--INPUTS
clock, clear : in std_logic;
--MEM control signals
data_format_in : in std_logic_vector(2 downto 0);
datamem_write_in : in std_logic;
jump_flag_in : in std_logic;
--WB control signals
mux0_sel_in : in std_logic_vector(1 downto 0);
reg_file_write_in : in std_logic;
reg_file_write_address_in : in std_logic_vector(4 downto 0);
--Data
ALU_output_in : in std_logic_vector(31 downto 0);
register_file_output_1_in : in std_logic_vector(31 downto 0);
ALU_branch_response_in : in std_logic;
instruction_address_in : in std_logic_vector(31 downto 0);
--OUTPUTS
--MEM control signals
data_format_out : out std_logic_vector(2 downto 0);
datamem_write_out : out std_logic;
jump_flag_out : out std_logic;
--WB control signals
mux0_sel_out : out std_logic_vector(1 downto 0);
reg_file_write_out : out std_logic;
reg_file_write_address_out : out std_logic_vector(4 downto 0);
--Data
ALU_output_out : out std_logic_vector(31 downto 0);
register_file_output_1_out : out std_logic_vector(31 downto 0);
ALU_branch_response_out : out std_logic;
instruction_address_out : out std_logic_vector(31 downto 0)
);
end EX_MEM_DIV;
architecture behavioral of EX_MEM_DIV is
--INTERNAL SIGNALS
--MEM control signals
signal data_format_input_signal : std_logic_vector(2 downto 0);
signal datamem_write_input_signal : std_logic;
signal jump_flag_input_signal : std_logic;
--WB control signals
signal mux0_sel_input_signal : std_logic_vector(1 downto 0);
signal reg_file_write_input_signal : std_logic;
signal reg_file_write_address_input_signal : std_logic_vector(4 downto 0);
--Data
signal ALU_output_input_signal : std_logic_vector(31 downto 0);
signal register_file_output_1_input_signal : std_logic_vector(31 downto 0);
signal ALU_branch_response_input_signal : std_logic;
signal instruction_address_input_signal : std_logic_vector(31 downto 0);
--MEM control signals
signal data_format_output_signal : std_logic_vector(2 downto 0);
signal datamem_write_output_signal : std_logic;
signal jump_flag_output_signal : std_logic;
--WB control signals
signal mux0_sel_output_signal : std_logic_vector(1 downto 0);
signal reg_file_write_output_signal : std_logic;
signal reg_file_write_address_output_signal : std_logic_vector(4 downto 0);
--Data
signal ALU_output_output_signal : std_logic_vector(31 downto 0);
signal register_file_output_1_output_signal : std_logic_vector(31 downto 0);
signal ALU_branch_response_output_signal : std_logic;
signal instruction_address_output_signal : std_logic_vector(31 downto 0);
begin
--INTERNAL REGISTERS
--MEM control signals
data_format_reg : reg3b port map(data_format_input_signal, '1', clock, clear, data_format_output_signal);
datamem_write_reg : reg1b port map(datamem_write_input_signal, '1', clock, clear, datamem_write_output_signal);
jump_flag_reg : reg1b port map(jump_flag_input_signal, '1', clock, clear, jump_flag_output_signal);
--WB control signals
mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal);
reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal);
reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal);
--Data
ALU_output_reg : reg32b port map(ALU_output_input_signal, '1', clock, clear, ALU_output_output_signal);
register_file_output_1_reg : reg32b port map(register_file_output_1_input_signal, '1', clock, clear, register_file_output_1_output_signal);
ALU_branch_respose_reg : reg1b port map(ALU_branch_response_input_signal, '1', clock, clear, ALU_branch_response_output_signal);
instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
--WIRING INPUT PORTS
--MEM control signals
data_format_input_signal <= data_format_in;
datamem_write_input_signal <= datamem_write_in;
jump_flag_input_signal <= jump_flag_in;
--WB control signals
mux0_sel_input_signal <= mux0_sel_in;
reg_file_write_input_signal <= reg_file_write_in;
reg_file_write_address_input_signal <= reg_file_write_address_in;
--Data
ALU_output_input_signal <= ALU_output_in;
register_file_output_1_input_signal <= register_file_output_1_in;
ALU_branch_response_input_signal <= ALU_branch_response_in;
instruction_address_input_signal <= instruction_address_in;
--WIRING OUTPUT PORTS
--MEM control signals
data_format_out <= data_format_output_signal;
datamem_write_out <= datamem_write_output_signal;
jump_flag_out <= jump_flag_output_signal;
--WB control signals
mux0_sel_out <= mux0_sel_output_signal;
reg_file_write_out <= reg_file_write_output_signal;
reg_file_write_address_out <= reg_file_write_address_output_signal;
--Data
ALU_output_out <= ALU_output_output_signal;
register_file_output_1_out <= register_file_output_1_output_signal;
ALU_branch_response_out <= ALU_branch_response_output_signal;
instruction_address_out <= instruction_address_output_signal;
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity ID_EX_DIV is
port (
--INPUTS
clock, clear : in std_logic;
--EX control signals
ALU_operation_in : in std_logic_vector(3 downto 0);
ALU_branch_in : in std_logic;
ALU_branch_control_in : in std_logic_vector(2 downto 0);
mux1_sel_in : in std_logic;
JTU_mux_sel_in : in std_logic;
--MEM control signals
data_format_in : in std_logic_vector(2 downto 0);
datamem_write_in : in std_logic;
jump_flag_in : in std_logic;
--WB control signals
mux0_sel_in : in std_logic_vector(1 downto 0);
reg_file_write_in : in std_logic;
reg_file_write_address_in : in std_logic_vector(4 downto 0);
--Read addresses to be given to the forwarding unit
register_file_read_address_0_in : in std_logic_vector(4 downto 0);
register_file_read_address_1_in : in std_logic_vector(4 downto 0);
--Data
register_file_output_0_in : in std_logic_vector(31 downto 0);
register_file_output_1_in : in std_logic_vector(31 downto 0);
immediate_in : in std_logic_vector(31 downto 0);
instruction_address_in : in std_logic_vector(31 downto 0);
--OUTPUTS
--EX control signals
ALU_operation_out : out std_logic_vector(3 downto 0);
ALU_branch_out : out std_logic;
ALU_branch_control_out : out std_logic_vector(2 downto 0);
mux1_sel_out : out std_logic;
JTU_mux_sel_out : out std_logic;
--MEM control signals
data_format_out : out std_logic_vector(2 downto 0);
datamem_write_out : out std_logic;
jump_flag_out : out std_logic;
--WB control signals
mux0_sel_out : out std_logic_vector(1 downto 0);
reg_file_write_out : out std_logic;
reg_file_write_address_out : out std_logic_vector(4 downto 0);
--Read addresses to be given to the forwarding unit
register_file_read_address_0_out : out std_logic_vector(4 downto 0);
register_file_read_address_1_out : out std_logic_vector(4 downto 0);
--Data
register_file_output_0_out : out std_logic_vector(31 downto 0);
register_file_output_1_out : out std_logic_vector(31 downto 0);
immediate_out : out std_logic_vector(31 downto 0);
instruction_address_out : out std_logic_vector(31 downto 0)
);
end ID_EX_DIV;
architecture behavioral of ID_EX_DIV is
--INTERNAL SIGNALS
--EX control signals
signal ALU_operation_input_signal : std_logic_vector(3 downto 0);
signal ALU_branch_input_signal : std_logic;
signal ALU_branch_control_input_signal : std_logic_vector(2 downto 0);
signal mux1_sel_input_signal : std_logic;
signal JTU_mux_sel_input_signal : std_logic;
--MEM control signals
signal data_format_input_signal : std_logic_vector(2 downto 0);
signal datamem_write_input_signal : std_logic;
signal jump_flag_input_signal : std_logic;
--WB control signals
signal mux0_sel_input_signal : std_logic_vector(1 downto 0);
signal reg_file_write_input_signal : std_logic;
signal reg_file_write_address_input_signal : std_logic_vector(4 downto 0);
--Data
signal register_file_output_0_input_signal : std_logic_vector(31 downto 0);
signal register_file_output_1_input_signal : std_logic_vector(31 downto 0);
signal immediate_input_signal : std_logic_vector(31 downto 0);
signal instruction_address_input_signal : std_logic_vector(31 downto 0);
--Read addresses to be given to the forwarding unit
signal register_file_read_address_0_input_signal : std_logic_vector(4 downto 0);
signal register_file_read_address_1_input_signal : std_logic_vector(4 downto 0);
--EX control signals
signal ALU_operation_output_signal : std_logic_vector(3 downto 0);
signal ALU_branch_output_signal : std_logic;
signal ALU_branch_control_output_signal : std_logic_vector(2 downto 0);
signal mux1_sel_output_signal : std_logic;
signal JTU_mux_sel_output_signal : std_logic;
--MEM control signals
signal data_format_output_signal : std_logic_vector(2 downto 0);
signal datamem_write_output_signal : std_logic;
signal jump_flag_output_signal : std_logic;
--WB control signals
signal mux0_sel_output_signal : std_logic_vector(1 downto 0);
signal reg_file_write_output_signal : std_logic;
signal reg_file_write_address_output_signal : std_logic_vector(4 downto 0);
--Data
signal register_file_output_0_output_signal : std_logic_vector(31 downto 0);
signal register_file_output_1_output_signal : std_logic_vector(31 downto 0);
signal immediate_output_signal : std_logic_vector(31 downto 0);
signal instruction_address_output_signal : std_logic_vector(31 downto 0);
--Read addresses to be given to the forwarding unit
signal register_file_read_address_0_output_signal : std_logic_vector(4 downto 0);
signal register_file_read_address_1_output_signal : std_logic_vector(4 downto 0);
begin
--INTERNAL REGISTERS
--EX control signals
ALU_operation_reg : reg4b port map(ALU_operation_input_signal, '1', clock, clear, ALU_operation_output_signal);
ALU_branch_reg : reg1b port map(ALU_branch_input_signal, '1', clock, clear, ALU_branch_output_signal);
ALU_branch_control_reg : reg3b port map(ALU_branch_control_input_signal, '1', clock, clear, ALU_branch_control_output_signal);
mux1_sel_reg : reg1b port map(mux1_sel_input_signal, '1', clock, clear, mux1_sel_output_signal);
JTU_mux_sel_reg : reg1b port map(JTU_mux_sel_input_signal, '1', clock, clear, JTU_mux_sel_output_signal);
--MEM control signals
data_format_reg : reg3b port map(data_format_input_signal, '1', clock, clear, data_format_output_signal);
datamem_write_reg : reg1b port map(datamem_write_input_signal, '1', clock, clear, datamem_write_output_signal);
jump_flag_reg : reg1b port map(jump_flag_input_signal, '1', clock, clear, jump_flag_output_signal);
--WB control signals
mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal);
reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal);
reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal);
--Data
register_file_output_0_reg : reg32b port map(register_file_output_0_input_signal, '1', clock, clear, register_file_output_0_output_signal);
register_file_output_1_reg : reg32b port map(register_file_output_1_input_signal, '1', clock, clear, register_file_output_1_output_signal);
immediate_reg : reg32b port map(immediate_input_signal, '1', clock, clear, immediate_output_signal);
instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
--Read addresses to be given to the forwarding unit
register_file_read_address_0_reg : reg5b port map(register_file_read_address_0_input_signal, '1', clock, clear, register_file_read_address_0_output_signal);
register_file_read_address_1_reg : reg5b port map(register_file_read_address_1_input_signal, '1', clock, clear, register_file_read_address_1_output_signal);
--WIRING INPUT PORTS
--EX control signals
ALU_operation_input_signal <= ALU_operation_in;
ALU_branch_input_signal <= ALU_branch_in;
ALU_branch_control_input_signal <= ALU_branch_control_in;
mux1_sel_input_signal <= mux1_sel_in;
JTU_mux_sel_input_signal <= JTU_mux_sel_in;
--MEM control signals
data_format_input_signal <= data_format_in;
datamem_write_input_signal <= datamem_write_in;
jump_flag_input_signal <= jump_flag_in;
--WB control signals
mux0_sel_input_signal <= mux0_sel_in;
reg_file_write_input_signal <= reg_file_write_in;
reg_file_write_address_input_signal <= reg_file_write_address_in;
--Data
register_file_output_0_input_signal <= register_file_output_0_in;
register_file_output_1_input_signal <= register_file_output_1_in;
immediate_input_signal <= immediate_in;
instruction_address_input_signal <= instruction_address_in;
--Read addresses to be given to the forwarding unit
register_file_read_address_0_input_signal <= register_file_read_address_0_in;
register_file_read_address_1_input_signal <= register_file_read_address_1_in;
--WIRING OUTPUT PORTS
--EX control signals
ALU_operation_out <= ALU_operation_output_signal;
ALU_branch_out <= ALU_branch_output_signal;
ALU_branch_control_out <= ALU_branch_control_output_signal;
mux1_sel_out <= mux1_sel_output_signal;
JTU_mux_sel_out <= JTU_mux_sel_output_signal;
--MEM control signals
data_format_out <= data_format_output_signal;
datamem_write_out <= datamem_write_output_signal;
jump_flag_out <= jump_flag_output_signal;
--WB control signals
mux0_sel_out <= mux0_sel_output_signal;
reg_file_write_out <= reg_file_write_output_signal;
reg_file_write_address_out <= reg_file_write_address_output_signal;
--Data
register_file_output_0_out <= register_file_output_0_output_signal;
register_file_output_1_out <= register_file_output_1_output_signal;
immediate_out <= immediate_output_signal;
instruction_address_out <= instruction_address_output_signal;
--Read addresses to be given to the forwarding unit
register_file_read_address_0_out <= register_file_read_address_0_output_signal;
register_file_read_address_1_out <= register_file_read_address_1_output_signal;
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity IF_ID_DIV is
port (
--INPUTS
clock, clear : in std_logic;
--Data
instruction_address_in : in std_logic_vector(31 downto 0);
instruction_data_in : in std_logic_vector(31 downto 0);
--OUTPUTS
--Data
instruction_address_out : out std_logic_vector(31 downto 0);
instruction_data_out : out std_logic_vector(31 downto 0)
);
end IF_ID_DIV;
architecture behavioral of IF_ID_DIV is
--INTERNAL SIGNALS
--Data
signal instruction_address_input_signal : std_logic_vector(31 downto 0);
signal instruction_data_input_signal : std_logic_vector(31 downto 0);
--Data
signal instruction_address_output_signal : std_logic_vector(31 downto 0);
signal instruction_data_output_signal : std_logic_vector(31 downto 0);
begin
--INTERNAL REGISTERS
--Data
instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
instruction_data_reg : reg32b port map(instruction_data_input_signal, '1', clock, clear, instruction_data_output_signal);
--WIRING OUTPUT PORTS
--Data
instruction_address_out <= instruction_address_output_signal;
instruction_data_out <= instruction_data_output_signal;
instruction_address_input_signal <= instruction_address_in;
instruction_data_input_signal <= instruction_data_in;
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity MEM_WB_DIV is
port (
--INPUTS
clock, clear : in std_logic;
--WB control signals
mux0_sel_in : in std_logic_vector(1 downto 0);
reg_file_write_in : in std_logic;
reg_file_write_address_in : in std_logic_vector(4 downto 0);
--Data
ALU_output_in : in std_logic_vector(31 downto 0);
datamem_output_in : in std_logic_vector(31 downto 0);
instruction_address_in : in std_logic_vector(31 downto 0);
--OUTPUTS
--WB control signals
mux0_sel_out : out std_logic_vector(1 downto 0);
reg_file_write_out : out std_logic;
reg_file_write_address_out : out std_logic_vector(4 downto 0);
--Data
ALU_output_out : out std_logic_vector(31 downto 0);
datamem_output_out : out std_logic_vector(31 downto 0);
instruction_address_out : out std_logic_vector(31 downto 0)
);
end MEM_WB_DIV;
architecture behavioral of MEM_WB_DIV is
--INTERNAL SIGNALS
--WB control signals
signal mux0_sel_input_signal : std_logic_vector(1 downto 0);
signal reg_file_write_input_signal : std_logic;
signal reg_file_write_address_input_signal : std_logic_vector(4 downto 0);
--Data
signal ALU_output_input_signal : std_logic_vector(31 downto 0);
signal datamem_output_input_signal : std_logic_vector(31 downto 0);
signal instruction_address_input_signal : std_logic_vector(31 downto 0);
--WB control signals
signal mux0_sel_output_signal : std_logic_vector(1 downto 0);
signal reg_file_write_output_signal : std_logic;
signal reg_file_write_address_output_signal : std_logic_vector(4 downto 0);
--Data
signal ALU_output_output_signal : std_logic_vector(31 downto 0);
signal datamem_output_output_signal : std_logic_vector(31 downto 0);
signal instruction_address_output_signal : std_logic_vector(31 downto 0);
begin
--INTERNAL REGISTERS
--WB control signals
mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal);
reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal);
reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal);
--Data
ALU_output_reg : reg32b port map(ALU_output_input_signal, '1', clock, clear, ALU_output_output_signal);
datamem_output_reg : reg32b port map(datamem_output_input_signal, '1', clock, clear, datamem_output_output_signal);
instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
--WIRING INPUT PORTS
--WB control signals
mux0_sel_input_signal <= mux0_sel_in;
reg_file_write_input_signal <= reg_file_write_in;
reg_file_write_address_input_signal <= reg_file_write_address_in;
--Data
ALU_output_input_signal <= ALU_output_in;
datamem_output_input_signal <= datamem_output_in;
instruction_address_input_signal <= instruction_address_in;
--WIRING OUTPUT PORTS
--WB control signals
mux0_sel_out <= mux0_sel_output_signal;
reg_file_write_out <= reg_file_write_output_signal;
reg_file_write_address_out <= reg_file_write_address_output_signal;
--Data
ALU_output_out <= ALU_output_output_signal;
datamem_output_out <= datamem_output_output_signal;
instruction_address_out <= instruction_address_output_signal;
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
port (
input_0 : in std_logic_vector(31 downto 0);
input_1 : in std_logic_vector(31 downto 0);
output_0 : out std_logic_vector(31 downto 0)
);
end adder;
architecture behavioral of adder is
signal internal_output : std_logic_vector (32 downto 0) := "000000000000000000000000000000000";
begin
process (input_0, input_1, internal_output) is
begin
internal_output <= std_logic_vector(signed(input_0(31) & input_0) + signed(input_1(31) & input_1));
end process;
output_0 <= internal_output(31 downto 0);
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity controller is
port (
clock : in std_logic;
reset : in std_logic;
instruction : in std_logic_vector(31 downto 0);
reg_file_read_address_0 : out std_logic_vector(4 downto 0);
reg_file_read_address_1 : out std_logic_vector(4 downto 0);
reg_file_write : out std_logic;
reg_file_write_address : out std_logic_vector(4 downto 0);
immediate : out std_logic_vector(31 downto 0);
ALU_operation : out std_logic_vector(3 downto 0);
ALU_branch : out std_logic;
ALU_branch_control : out std_logic_vector(2 downto 0);
JTU_mux_sel : out std_logic;
data_format : out std_logic_vector(2 downto 0);
datamem_write : out std_logic;
jump_flag : out std_logic;
mux0_sel : out std_logic_vector(1 downto 0);
mux1_sel : out std_logic
);
end entity controller;
architecture Behavioral of controller is
type operational_states is (normal);
signal current_state, next_state : operational_states := normal;
type instruction_cluster is (INVALID, LOAD, STORE, MADD, BRANCH, LOAD_FP, STORE_FP, MSUB, JALR, NMSUB, MISC_MEM, AMO, NMADD, JAL, OP_IMM, OP, OP_FP, SYSTEM, AUIPC, LUI, OP_IMM_32, OP_32);
signal decoded_cluster : instruction_cluster;
type opcode is (INVALID, LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW,
ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, inst_SLL, SLT, SLTU, inst_XOR, inst_SRL, inst_SRA, inst_OR, inst_AND, FENCE,
FENCEI, EXALL, EBREAK, CSRRW, CSRRS, CSRRC, CSRRSI, CSRRCI);
signal decoded_opcode : opcode;
signal fetched_instruction : std_logic_vector (31 downto 0) := X"00000000";
signal internal_immediate : std_logic_vector (31 downto 0) := X"00000000";
signal internal_reg_file_read_address_0 : std_logic_vector(4 downto 0) := "00000";
signal internal_reg_file_read_address_1 : std_logic_vector(4 downto 0) := "00000";
signal internal_reg_file_write : std_logic := '0';
signal internal_reg_file_write_address : std_logic_vector(4 downto 0) := "00000";
signal internal_PC_operation : std_logic_vector(2 downto 0) := "000";
signal internal_ALU_operation : std_logic_vector(3 downto 0) := "0000";
signal internal_ALU_branch : std_logic := '0';
signal internal_ALU_branch_control : std_logic_vector(2 downto 0) := "000";
signal internal_JTU_mux_sel : std_logic;
signal internal_data_format : std_logic_vector(2 downto 0) := "000";
signal internal_datamem_write : std_logic := '0';
signal internal_jump_flag : std_logic := '0';
signal internal_mux0_sel : std_logic_vector(1 downto 0) := "00";
signal internal_mux1_sel : std_logic := '0';
begin
synchronism : process (clock, reset)
begin
if (reset = '1') then
current_state <= normal;
elsif rising_edge(clock) then
current_state <= next_state;
end if;
end process;
logic : process (fetched_instruction, decoded_cluster, decoded_opcode, current_state)
begin
case (current_state) is
-- when start => --This states exists to clean the existing mess and restart the processor
-- internal_reg_file_read_address_0 <= "00000";
-- internal_reg_file_read_address_1 <= "00000";
-- internal_reg_file_write <= '0';
-- internal_reg_file_write_address <= "00000";
-- internal_immediate <= X"00000000";
-- internal_PC_operation <= "000";
-- internal_ALU_operation <= "0000"; --unused number to make the ALU output 0
-- internal_ALU_branch <= '0';
-- internal_ALU_branch_control <= "000";
-- internal_data_format <= "000";
-- internal_datamem_write <= '0';
-- internal_mux0_sel <= "00";
-- internal_mux1_sel <= '0';
-- next_state <= normal;
when normal =>
if fetched_instruction(1 downto 0) = "00" then
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
else
case (fetched_instruction(4 downto 2)) is
when "000" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --LOAD
decoded_cluster <= LOAD;
case (fetched_instruction(14 downto 12)) is --funct3
when "000" => --Load Byte
decoded_opcode <= LB;
when "001" => --Load Half-Word
decoded_opcode <= LH;
when "010" => --Load Word
decoded_opcode <= LW;
when "100" => --Load Byte Unsigned
decoded_opcode <= LBU;
when "101" => --Load Hald-Word Unsigned
decoded_opcode <= LHU;
when others =>
decoded_opcode <= INVALID;
end case;
when "01" => --STORE
decoded_cluster <= STORE;
case (fetched_instruction(14 downto 12)) is --funct3
when "000" => --Store Byte
decoded_opcode <= SB;
when "001" => --Store Half-Word
decoded_opcode <= SH;
when "010" => --Store Word
decoded_opcode <= SW;
when others =>
decoded_opcode <= INVALID;
end case;
when "10" => --MADD
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --BRANCH
decoded_cluster <= BRANCH;
case (fetched_instruction(14 downto 12)) is --funct3
when "000" => --Branch if equal
decoded_opcode <= BEQ;
when "001" => --Branch if not equal
decoded_opcode <= BNE;
when "100" => --Branch if lower than
decoded_opcode <= BLT;
when "101" => --Branch if greater or equal
decoded_opcode <= BGE;
when "110" => --Branch if lower than unsigned
decoded_opcode <= BLTU;
when "111" => --Branch if greater or equal unsigned
decoded_opcode <= BGEU;
when others =>
decoded_opcode <= INVALID;
end case;
end case;
when "001" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --LOAD-FP
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "01" => --STORE-FP
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "10" => --MSUB
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --JALR
decoded_cluster <= JALR;
decoded_opcode <= JALR;
end case;
when "010" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --Custom 0
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "01" => --Custom 1
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "10" => --NMSUB
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --Reserved
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
end case;
when "011" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --MISC-MEM
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "01" => --AMO
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "10" => --NMADD
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --JAL
decoded_cluster <= JAL;
decoded_opcode <= JAL;
end case;
when "100" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --OP-IMM
decoded_cluster <= OP_IMM;
case (fetched_instruction(14 downto 12)) is --funct3
when "000" => --Add immediate
decoded_opcode <= ADDI;
when "010" => --Set less than immediate
decoded_opcode <= SLTI;
when "011" => --Set less than immediate unsigned
decoded_opcode <= SLTIU;
when "100" => --XOR immediate
decoded_opcode <= XORI;
when "110" => --OR immediate
decoded_opcode <= ORI;
when "111" => --AND immediate
decoded_opcode <= ANDI;
when "001" => --Shift left logical immediate
decoded_opcode <= SLLI;
when "101" => --Shift right immediate
case (fetched_instruction(30)) is
when '0' => --Shift right logical immediate
decoded_opcode <= SRLI;
when '1' => --Shift right arithmetic immediate
decoded_opcode <= SRAI;
end case;
when others =>
decoded_opcode <= INVALID;
end case;
when "01" => --OP
decoded_cluster <= OP;
case (fetched_instruction(14 downto 12)) is --funct3
when "000" => --ADD or SUB
case (fetched_instruction(30)) is
when '0' => --Add
decoded_opcode <= ADD;
when '1' => --Sub
decoded_opcode <= SUB;
end case;
when "001" => --Shift left logical
decoded_opcode <= inst_SLL;
when "010" => --Set less than
decoded_opcode <= SLT;
when "011" => --Set less than unsigned
decoded_opcode <= SLTU;
when "100" => --XOR
decoded_opcode <= inst_XOR;
when "101" => --Shift right
case (fetched_instruction(30)) is
when '0' => --Shift right logical
decoded_opcode <= inst_SRL;
when '1' => --Shift right arithmetic
decoded_opcode <= inst_SRA;
end case;
when "110" => --OR
decoded_opcode <= inst_OR;
when "111" => --AND
decoded_opcode <= inst_AND;
end case;
when "10" => --OP-FP
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --SYSTEM
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
end case;
when "101" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --AUIPC
decoded_cluster <= AUIPC;
decoded_opcode <= AUIPC;
when "01" => --LUI
decoded_cluster <= LUI;
decoded_opcode <= LUI;
when "10" => --Reserved
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --Reserved
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
end case;
when "110" =>
case (fetched_instruction(6 downto 5)) is
when "00" => --OP-IMM-32
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "01" => --OP-32
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "10" => --rv128
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
when "11" => --rv128
decoded_cluster <= INVALID;
decoded_opcode <= INVALID;
end case;
when others =>
end case;
end if;
case (decoded_cluster) is
when INVALID =>
internal_reg_file_read_address_0 <= "00000";
internal_reg_file_read_address_1 <= "00000";
internal_reg_file_write <= '0';
internal_reg_file_write_address <= "00000";
internal_immediate <= X"00000000";
internal_ALU_operation <= "0000"; --random unused number to make the ALU output 0
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '0';
next_state <= normal;
when LOAD =>
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
internal_reg_file_read_address_1 <= "00000";
internal_reg_file_write <= '1'; --regfile is only lodaded on write_back
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector("00000000000000000000" & fetched_instruction(31 downto 20));
internal_ALU_operation <= "0000";
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000"; --BEQ, BNE, BLT, BGE, BLTU, BGEU
internal_JTU_mux_sel <= '0';
internal_data_format <= std_logic_vector(fetched_instruction(14 downto 12)); --LB, LH, LW, LBU, LHU
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "01";
internal_mux1_sel <= '1';
next_state <= normal;
when STORE =>
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
internal_reg_file_write <= '0';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector("00000000000000000000" & fetched_instruction(31 downto 25) & fetched_instruction(11 downto 7));
internal_ALU_operation <= "0000";
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000"; --BEQ, BNE, BLT, BGE, BLTU, BGEU
internal_JTU_mux_sel <= '0';
internal_data_format <= std_logic_vector(fetched_instruction(14 downto 12)); --SB, SH, SW
internal_datamem_write <= '1'; --memory is only written on memory_access
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '1';
next_state <= normal;
when BRANCH =>
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
internal_reg_file_write <= '0';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector("00000000000000000" & fetched_instruction(31) & fetched_instruction(7) & fetched_instruction(30 downto 25) & fetched_instruction(11 downto 6) & '0');
internal_ALU_operation <= "0000";
internal_ALU_branch <= '1';
internal_ALU_branch_control <= std_logic_vector(fetched_instruction(14 downto 12)); --BEQ, BNE, BLT, BGE, BLTU, BGEU
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '0';
next_state <= normal;
when JALR =>
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
internal_reg_file_read_address_1 <= "00000";
internal_reg_file_write <= '1';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector(shift_right(signed(fetched_instruction(31 downto 20) & "00000000000000000000"), 20));
internal_ALU_operation <= "0000";
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '1';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '1';
internal_mux0_sel <= "10";
internal_mux1_sel <= '0';
next_state <= normal;
when JAL =>
internal_reg_file_read_address_0 <= "00000";
internal_reg_file_read_address_1 <= "00000";
internal_reg_file_write <= '1';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector(shift_right(signed(fetched_instruction(31) & fetched_instruction(19 downto 12) & fetched_instruction(20) & fetched_instruction(30 downto 21) & '0' & "00000000000"), 11));
internal_ALU_operation <= "0000";
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '1';
internal_mux0_sel <= "10";
internal_mux1_sel <= '0';
next_state <= normal;
when OP_IMM => --ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
internal_reg_file_write <= '1';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '1';
case (decoded_opcode) is
when ADDI | SLTI | SLTIU =>
internal_ALU_operation <= std_logic_vector('0' & fetched_instruction(14 downto 12));
internal_immediate <= std_logic_vector(shift_right(signed(fetched_instruction(31 downto 20) & "00000000000000000000"), 20));
when XORI | ORI | ANDI =>
internal_ALU_operation <= std_logic_vector('0' & fetched_instruction(14 downto 12));
internal_immediate <= std_logic_vector("00000000000000000000" & fetched_instruction(31 downto 20));
when SLLI =>
internal_ALU_operation <= std_logic_vector('0' & fetched_instruction(14 downto 12));
internal_immediate <= std_logic_vector("000000000000000000000000000" & fetched_instruction(24 downto 20));
when SRLI | SRAI =>
internal_ALU_operation <= std_logic_vector(fetched_instruction(30) & fetched_instruction(14 downto 12));
internal_immediate <= std_logic_vector("000000000000000000000000000" & fetched_instruction(24 downto 20));
when others =>
end case;
next_state <= normal;
when OP =>
internal_reg_file_read_address_0 <= fetched_instruction(19 downto 15);
internal_reg_file_read_address_1 <= fetched_instruction(24 downto 20);
internal_reg_file_write <= '1';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= X"00000000";
internal_ALU_operation <= std_logic_vector(fetched_instruction(30) & fetched_instruction(14 downto 12));
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '0';
next_state <= normal;
when AUIPC =>
internal_reg_file_read_address_0 <= "00000";
internal_reg_file_read_address_1 <= "00000";
internal_reg_file_write <= '1';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector(fetched_instruction(31 downto 12) & "000000000000");
internal_ALU_operation <= "0000";
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '0';
next_state <= normal;
when LUI =>
internal_reg_file_read_address_0 <= "00000";
internal_reg_file_read_address_1 <= "00000";
internal_reg_file_write <= '1';
internal_reg_file_write_address <= fetched_instruction(11 downto 7);
internal_immediate <= std_logic_vector(fetched_instruction(31 downto 12) & "000000000000");
internal_ALU_operation <= "0000";
internal_ALU_branch <= '0';
internal_ALU_branch_control <= "000";
internal_JTU_mux_sel <= '0';
internal_data_format <= "000";
internal_datamem_write <= '0';
internal_jump_flag <= '0';
internal_mux0_sel <= "00";
internal_mux1_sel <= '1';
next_state <= normal;
when others =>
end case;
end case;
end process;
fetched_instruction <= instruction;
reg_file_read_address_0 <= internal_reg_file_read_address_0;
reg_file_read_address_1 <= internal_reg_file_read_address_1;
reg_file_write <= internal_reg_file_write;
reg_file_write_address <= internal_reg_file_write_address;
immediate <= internal_immediate;
ALU_operation <= internal_ALU_operation;
ALU_branch <= internal_ALU_branch;
ALU_branch_control <= internal_ALU_branch_control;
JTU_mux_sel <= internal_JTU_mux_sel;
data_format <= internal_data_format;
datamem_write <= internal_datamem_write;
jump_flag <= internal_jump_flag;
mux0_sel <= internal_mux0_sel;
mux1_sel <= internal_mux1_sel;
end architecture Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity datamem is
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector(15 downto 0);
input_data : in std_logic_vector(7 downto 0);
output_data : out std_logic_vector(7 downto 0)
);
end datamem;
architecture behavioural of datamem is
type ram_type is array (65536 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type;
begin
process (clock, write_enable)
begin
if falling_edge(clock) and write_enable = '1' then
RAM(conv_integer(address)) <= input_data;
end if;
end process;
output_data <= RAM(conv_integer(address));
end behavioural;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity datamem_interface is
port (
input_data : in std_logic_vector(31 downto 0);
byte_address : in std_logic_vector(31 downto 0);
data_format : in std_logic_vector(2 downto 0);
clock, load, clear : in std_logic;
output_data : out std_logic_vector(31 downto 0)
);
end entity datamem_interface;
architecture behavioural of datamem_interface is
signal internal_load : std_logic_vector(3 downto 0);
signal memory_input_0 : std_logic_vector(7 downto 0);
signal memory_input_1 : std_logic_vector(7 downto 0);
signal memory_input_2 : std_logic_vector(7 downto 0);
signal memory_input_3 : std_logic_vector(7 downto 0);
signal memory_output_0 : std_logic_vector(7 downto 0);
signal memory_output_1 : std_logic_vector(7 downto 0);
signal memory_output_2 : std_logic_vector(7 downto 0);
signal memory_output_3 : std_logic_vector(7 downto 0);
signal membank_address : std_logic_vector(31 downto 0);
signal byte_starting_position : std_logic_vector(1 downto 0) := "00";
begin
membank_address_acquirement : process (input_data, byte_address, data_format, load, byte_starting_position, memory_output_0, memory_output_1, memory_output_2, memory_output_3)
begin
membank_address <= std_logic_vector(shift_right(unsigned(byte_address), 2)); --Dividing by 4 while throwing away non-integer information
byte_starting_position <= byte_address(1 downto 0); --Last 2 bits to know which of the 4 memory banks we should access
if (load = '1') then --writing to memory, data needs to go to the correct place and stay aligned
case data_format is
when "000" => --Word operation, don't do anything to the input
if (byte_starting_position = "00") then
internal_load <= "1111";
memory_input_3 <= input_data(31 downto 24);
memory_input_2 <= input_data(23 downto 16);
memory_input_1 <= input_data(15 downto 8);
memory_input_0 <= input_data(7 downto 0);
else
internal_load <= "0000";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= X"00";
end if;
when "001" => --Signed halfword
if (byte_starting_position = "00") then
internal_load <= "0011";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= input_data(15 downto 8);
memory_input_0 <= input_data(7 downto 0);
elsif (byte_starting_position = "10") then
internal_load <= "1100";
memory_input_3 <= input_data(15 downto 8);
memory_input_2 <= input_data(7 downto 0);
memory_input_1 <= X"00";
memory_input_0 <= X"00";
else
internal_load <= "0000";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= X"00";
end if;
when "010" => --Unsigned halfword
if (byte_starting_position = "00") then
internal_load <= "0011";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= input_data(15 downto 8);
memory_input_0 <= input_data(7 downto 0);
elsif (byte_starting_position = "10") then
internal_load <= "1100";
memory_input_3 <= input_data(15 downto 8);
memory_input_2 <= input_data(7 downto 0);
memory_input_1 <= X"00";
memory_input_0 <= X"00";
else
internal_load <= "0000";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= X"00";
end if;
when "011" => --Signed byte
if (byte_starting_position = "00") then
internal_load <= "0001";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= input_data(7 downto 0);
elsif (byte_starting_position = "01") then
internal_load <= "0010";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= input_data(7 downto 0);
memory_input_0 <= X"00";
elsif (byte_starting_position = "10") then
internal_load <= "0100";
memory_input_3 <= X"00";
memory_input_2 <= input_data(7 downto 0);
memory_input_1 <= X"00";
memory_input_0 <= X"00";
elsif (byte_starting_position = "11") then
internal_load <= "1000";
memory_input_3 <= input_data(7 downto 0);
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= X"00";
internal_load <= "0000";
end if;
when "100" => --Unsigned byte
if (byte_starting_position = "00") then
internal_load <= "0001";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= input_data(7 downto 0);
elsif (byte_starting_position = "01") then
internal_load <= "0010";
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= input_data(7 downto 0);
memory_input_0 <= X"00";
elsif (byte_starting_position = "10") then
internal_load <= "0100";
memory_input_3 <= X"00";
memory_input_2 <= input_data(7 downto 0);
memory_input_1 <= X"00";
memory_input_0 <= X"00";
elsif (byte_starting_position = "11") then
internal_load <= "1000";
memory_input_3 <= input_data(7 downto 0);
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= X"00";
internal_load <= "0000";
end if;
when others =>
memory_input_3 <= X"00";
memory_input_2 <= X"00";
memory_input_1 <= X"00";
memory_input_0 <= X"00";
internal_load <= "0000";
end case;
else --reading operation, data needs to be formatted to be sent to internal registers in the registerfile
internal_load <= "0000";
case data_format is
when "000" => --Word operation, don't do anything to the input
if (byte_starting_position = "00") then
output_data <= std_logic_vector(memory_output_3 & memory_output_2 & memory_output_1 & memory_output_0);
else
output_data <= X"00000000";
end if;
when "001" => --Signed halfword, discard upper half and bit-extend
if (byte_starting_position = "00") then
output_data <= std_logic_vector(shift_right(signed(std_logic_vector(memory_output_1 & memory_output_0 & X"0000")), 16));
elsif (byte_starting_position = "10") then
output_data <= std_logic_vector(shift_right(signed(std_logic_vector(memory_output_3 & memory_output_2 & X"0000")), 16));
else
output_data <= X"00000000";
end if;
when "010" => --Unsigned halfword, discard upper half then complete the array with 0s
if (byte_starting_position = "00") then
output_data <= std_logic_vector(X"0000" & memory_output_1 & memory_output_0);
elsif (byte_starting_position = "10") then
output_data <= std_logic_vector(X"0000" & memory_output_3 & memory_output_2);
else
output_data <= X"00000000";
end if;
when "011" => --Signed byte, discard upper 24 bits and bit-extend
if (byte_starting_position = "00") then
output_data <= std_logic_vector(shift_right(signed(std_logic_vector(memory_output_0 & X"000000")), 24));
elsif (byte_starting_position = "01") then
output_data <= std_logic_vector(shift_right(signed(std_logic_vector(memory_output_1 & X"000000")), 24));
elsif (byte_starting_position = "10") then
output_data <= std_logic_vector(shift_right(signed(std_logic_vector(memory_output_2 & X"000000")), 24));
elsif (byte_starting_position = "11") then
output_data <= std_logic_vector(shift_right(signed(std_logic_vector(memory_output_3 & X"000000")), 24));
end if;
when "100" => --Unsigned byte, discard upper 24 bits then complete with 0s
if (byte_starting_position = "00") then
output_data <= std_logic_vector(X"000000" & memory_output_0);
elsif (byte_starting_position = "01") then
output_data <= std_logic_vector(X"000000" & memory_output_1);
elsif (byte_starting_position = "10") then
output_data <= std_logic_vector(X"000000" & memory_output_2);
elsif (byte_starting_position = "11") then
output_data <= std_logic_vector(X"000000" & memory_output_3);
end if;
when others =>
output_data <= X"00000000";
end case;
end if;
end process;
-- datamem_3 : datamem port map(membank_address(7 downto 0), clock, memory_input_3, internal_load(3), memory_output_3); --USE THIS FOR ALTERA MEMORY
-- datamem_2 : datamem port map(membank_address(7 downto 0), clock, memory_input_2, internal_load(2), memory_output_2);
-- datamem_1 : datamem port map(membank_address(7 downto 0), clock, memory_input_1, internal_load(1), memory_output_1);
-- datamem_0 : datamem port map(membank_address(7 downto 0), clock, memory_input_0, internal_load(0), memory_output_0);
-- datamem_3 : datamem port map(clock, clear, internal_load(3), memory_input_3, membank_address(7 downto 0), memory_output_3); --USE THIS FOR A DATAMEM DERIVED FROM MY REGFILE
-- datamem_2 : datamem port map(clock, clear, internal_load(2), memory_input_2, membank_address(7 downto 0), memory_output_2);
-- datamem_1 : datamem port map(clock, clear, internal_load(1), memory_input_1, membank_address(7 downto 0), memory_output_1);
-- datamem_0 : datamem port map(clock, clear, internal_load(0), memory_input_0, membank_address(7 downto 0), memory_output_0);
datamem_3 : datamem port map(clock, internal_load(3), membank_address(15 downto 0), memory_input_3, memory_output_3);
datamem_2 : datamem port map(clock, internal_load(2), membank_address(15 downto 0), memory_input_2, memory_output_2);
datamem_1 : datamem port map(clock, internal_load(1), membank_address(15 downto 0), memory_input_1, memory_output_1);
datamem_0 : datamem port map(clock, internal_load(0), membank_address(15 downto 0), memory_input_0, memory_output_0);
end architecture behavioural;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity datapath is
port (
clock : in std_logic;
reset : in std_logic;
reg_file_read_address_0 : in std_logic_vector(4 downto 0);
reg_file_read_address_1 : in std_logic_vector(4 downto 0);
reg_file_write : in std_logic;
reg_file_write_address : in std_logic_vector(4 downto 0);
immediate : in std_logic_vector(31 downto 0);
ALU_operation : in std_logic_vector(3 downto 0);
ALU_branch : in std_logic;
ALU_branch_control : in std_logic_vector(2 downto 0);
JTU_mux_sel : in std_logic;
data_format : in std_logic_vector(2 downto 0);
datamem_write : in std_logic;
jump_flag : in std_logic;
mux0_sel : in std_logic_vector(1 downto 0);
mux1_sel : in std_logic;
instruction : buffer std_logic_vector(31 downto 0); --change it back to output later
debug_instruction_address : out std_logic_vector(31 downto 0);
debug_regfile_x31_output : out std_logic_vector(31 downto 0);
debug_regfile_x1_output : out std_logic_vector(31 downto 0);
debug_regfile_x2_output : out std_logic_vector(31 downto 0);
debug_ALU_output : out std_logic_vector(31 downto 0);
debug_ALU_input_0 : out std_logic_vector(31 downto 0);
debug_ALU_input_1 : out std_logic_vector(31 downto 0);
debug_forward_mux_0 : out std_logic_vector(2 downto 0);
debug_forward_mux_1 : out std_logic_vector(2 downto 0);
debug_reg_file_read_address_0_ID_EXE : out std_logic_vector(4 downto 0);
debug_reg_file_write_address_EX_MEM : out std_logic_vector(4 downto 0);
debug_mux0_sel_MEM_WB : out std_logic_vector(1 downto 0);
debug_reg_file_write_MEM_WB : out std_logic;
debug_reg_file_write_address_MEM_WB : out std_logic_vector(4 downto 0);
debug_ALU_output_MEM_WB : out std_logic_vector(31 downto 0);
debug_ALU_output_EX_MEM : out std_logic_vector(31 downto 0);
debug_register_file_output_0 : out std_logic_vector(31 downto 0);
debug_register_file_output_1 : out std_logic_vector(31 downto 0);
debug_register_file_output_0_ID_EX : out std_logic_vector(31 downto 0);
debug_register_file_output_1_ID_EX : out std_logic_vector(31 downto 0);
debug_instruction : out std_logic_vector(31 downto 0)
);
end entity datapath;
architecture structural of datapath is
signal PC_output : std_logic_vector(31 downto 0); -- use this as your progmem input when your memory does not have a registered input
signal PC_next_address : std_logic_vector(31 downto 0); --use this when it does
signal progmem_output : std_logic_vector(31 downto 0);
signal flushing_unit_output : std_logic;
signal mux_0_output : std_logic_vector(31 downto 0);
signal mux_1_output : std_logic_vector(31 downto 0);
signal register_file_output_0 : std_logic_vector(31 downto 0);
signal register_file_output_1 : std_logic_vector(31 downto 0);
signal ALU_branch_response : std_logic;
signal ALU_output : std_logic_vector(31 downto 0);
signal datamem_output : std_logic_vector(31 downto 0);
signal instruction_address_IF_ID : std_logic_vector(31 downto 0);
signal ALU_operation_ID_EX : std_logic_vector(3 downto 0);
signal ALU_branch_ID_EX : std_logic;
signal ALU_branch_control_ID_EX : std_logic_vector(2 downto 0);
signal mux1_sel_ID_EX : std_logic;
signal JTU_mux_sel_ID_EX : std_logic;
signal data_format_ID_EX : std_logic_vector(2 downto 0);
signal datamem_write_ID_EX : std_logic;
signal jump_flag_ID_EX : std_logic;
signal mux0_sel_ID_EX : std_logic_vector(1 downto 0);
signal reg_file_write_ID_EX : std_logic;
signal reg_file_write_address_ID_EX : std_logic_vector(4 downto 0);
signal register_file_read_address_0_ID_EX : std_logic_vector (4 downto 0);
signal register_file_read_address_1_ID_EX : std_logic_vector (4 downto 0);
signal register_file_output_0_ID_EX : std_logic_vector(31 downto 0);
signal register_file_output_1_ID_EX : std_logic_vector(31 downto 0);
signal immediate_ID_EX : std_logic_vector(31 downto 0);
signal instruction_address_ID_EX : std_logic_vector(31 downto 0);
signal forward_mux_0_control : std_logic_vector(2 downto 0);
signal forward_mux_1_control : std_logic_vector(2 downto 0);
signal forward_mux_0_output : std_logic_vector(31 downto 0);
signal forward_mux_1_output : std_logic_vector(31 downto 0);
signal JTU_output : std_logic_vector(31 downto 0);
signal data_format_EX_MEM : std_logic_vector(2 downto 0);
signal datamem_write_EX_MEM : std_logic;
signal jump_flag_EX_MEM : std_logic;
signal mux0_sel_EX_MEM : std_logic_vector(1 downto 0);
signal reg_file_write_EX_MEM : std_logic;
signal reg_file_write_address_EX_MEM : std_logic_vector(4 downto 0);
signal ALU_branch_response_EX_MEM : std_logic;
signal ALU_output_EX_MEM : std_logic_vector(31 downto 0);
signal register_file_output_1_EX_MEM : std_logic_vector(31 downto 0);
signal instruction_address_EX_MEM : std_logic_vector(31 downto 0);
signal mux0_sel_MEM_WB : std_logic_vector(1 downto 0);
signal reg_file_write_MEM_WB : std_logic;
signal reg_file_write_address_MEM_WB : std_logic_vector(4 downto 0);
signal ALU_output_MEM_WB : std_logic_vector(31 downto 0);
signal datamem_output_MEM_WB : std_logic_vector(31 downto 0);
signal instruction_address_MEM_WB : std_logic_vector(31 downto 0);
signal debug_regfile_x31_output_signal : std_logic_vector(31 downto 0);
signal debug_regfile_x1_output_signal : std_logic_vector(31 downto 0);
signal debug_regfile_x2_output_signal : std_logic_vector(31 downto 0);
begin
program_counter_0 : program_counter port map(reset, clock, ALU_branch_response or jump_flag_ID_EX, std_logic_vector(unsigned(PC_output) + 4), JTU_output, PC_next_address, PC_output);
progmem_module_0 : progmem_interface port map(clock, PC_next_address, progmem_output);
IF_ID_PLR : IF_ID_DIV port map(clock, reset or flushing_unit_output, PC_output, progmem_output, instruction_address_IF_ID, instruction);
mux_0 : mux_3_1 port map(mux0_sel_MEM_WB, ALU_output_MEM_WB, datamem_output_MEM_WB, std_logic_vector(unsigned(instruction_address_MEM_WB) + 4), mux_0_output);
register_file_0 : register_file port map(mux_0_output, reg_file_write_address_MEM_WB, reg_file_read_address_0, reg_file_read_address_1, reg_file_write_MEM_WB, clock, reset, register_file_output_0, register_file_output_1, debug_regfile_x31_output_signal, debug_regfile_x1_output_signal, debug_regfile_x2_output_signal);
ID_EX_PLR : ID_EX_DIV port map(clock, reset or flushing_unit_output, ALU_operation, ALU_branch, ALU_branch_control, mux1_sel, JTU_mux_sel, data_format, datamem_write, jump_flag, mux0_sel, reg_file_write, reg_file_write_address, reg_file_read_address_0, reg_file_read_address_1, register_file_output_0, register_file_output_1, immediate, instruction_address_IF_ID, ALU_operation_ID_EX, ALU_branch_ID_EX, ALU_branch_control_ID_EX, mux1_sel_ID_EX, JTU_mux_sel_ID_EX, data_format_ID_EX, datamem_write_ID_EX, jump_flag_ID_EX, mux0_sel_ID_EX, reg_file_write_ID_EX, reg_file_write_address_ID_EX, register_file_read_address_0_ID_EX, register_file_read_address_1_ID_EX, register_file_output_0_ID_EX, register_file_output_1_ID_EX, immediate_ID_EX, instruction_address_ID_EX);
FU_0 : forwarding_unit port map(register_file_read_address_0_ID_EX, register_file_read_address_1_ID_EX, reg_file_write_EX_MEM, reg_file_write_address_EX_MEM, mux0_sel_EX_MEM, reg_file_write_MEM_WB, reg_file_write_address_MEM_WB, mux0_sel_MEM_WB, forward_mux_0_control, forward_mux_1_control);
forward_mux_0 : mux_5_1 port map(forward_mux_0_control, register_file_output_0_ID_EX, ALU_output_EX_MEM, datamem_output, ALU_output_MEM_WB, datamem_output_MEM_WB, forward_mux_0_output);
forward_mux_1 : mux_5_1 port map(forward_mux_1_control, register_file_output_1_ID_EX, ALU_output_EX_MEM, datamem_output, ALU_output_MEM_WB, datamem_output_MEM_WB, forward_mux_1_output);
mux_1 : mux_2_1 port map(mux1_sel_ID_EX, forward_mux_1_output, immediate_ID_EX, mux_1_output);
ALU_0 : ALU port map(forward_mux_0_output, mux_1_output, ALU_operation_ID_EX, ALU_branch_ID_EX, ALU_branch_control_ID_EX, ALU_branch_response, ALU_output);
JTU_0 : jump_target_unit port map(JTU_mux_sel_ID_EX, instruction_address_ID_EX, register_file_output_0_ID_EX, immediate_ID_EX, JTU_output);
EX_MEM_PLR : EX_MEM_DIV port map(clock, reset, data_format_ID_EX, datamem_write_ID_EX, jump_flag_ID_EX, mux0_sel_ID_EX, reg_file_write_ID_EX, reg_file_write_address_ID_EX, ALU_output, forward_mux_1_output, ALU_branch_response, instruction_address_ID_EX, data_format_EX_MEM, datamem_write_EX_MEM, jump_flag_EX_MEM, mux0_sel_EX_MEM, reg_file_write_EX_MEM, reg_file_write_address_EX_MEM, ALU_output_EX_MEM, register_file_output_1_EX_MEM, ALU_branch_response_EX_MEM, instruction_address_EX_MEM);
FLUSH : flushing_unit port map(reset, clock, ALU_branch_response_EX_MEM or jump_flag_EX_MEM, flushing_unit_output);
datamem_module_0 : datamem_interface port map(register_file_output_1_EX_MEM, ALU_output_EX_MEM, data_format_EX_MEM, clock, datamem_write_EX_MEM, reset, datamem_output);
MEM_WB_PLR : MEM_WB_DIV port map(clock, reset, mux0_sel_EX_MEM, reg_file_write_EX_MEM, reg_file_write_address_EX_MEM, ALU_output_EX_MEM, datamem_output, instruction_address_EX_MEM, mux0_sel_MEM_WB, reg_file_write_MEM_WB, reg_file_write_address_MEM_WB, ALU_output_MEM_WB, datamem_output_MEM_WB, instruction_address_MEM_WB);
debug_instruction_address <= PC_output;
debug_regfile_x31_output <= debug_regfile_x31_output_signal;
debug_regfile_x1_output <= debug_regfile_x1_output_signal;
debug_regfile_x2_output <= debug_regfile_x2_output_signal;
debug_ALU_output <= ALU_output;
debug_ALU_input_0 <= forward_mux_0_output;
debug_ALU_input_1 <= mux_1_output;
debug_forward_mux_0 <= forward_mux_0_control;
debug_forward_mux_1 <= forward_mux_1_control;
debug_reg_file_read_address_0_ID_EXE <= register_file_read_address_0_ID_EX;
debug_reg_file_write_address_EX_MEM <= reg_file_write_address_EX_MEM;
debug_mux0_sel_MEM_WB <= mux0_sel_MEM_WB;
debug_reg_file_write_MEM_WB <= reg_file_write_MEM_WB;
debug_reg_file_write_address_MEM_WB <= reg_file_write_address_MEM_WB;
debug_ALU_output_MEM_WB <= ALU_output_MEM_WB;
debug_ALU_output_EX_MEM <= ALU_output_EX_MEM;
debug_register_file_output_0 <= register_file_output_0;
debug_register_file_output_1 <= register_file_output_1;
debug_register_file_output_0_ID_EX <= register_file_output_0_ID_EX;
debug_register_file_output_1_ID_EX <= register_file_output_1_ID_EX;
debug_instruction <= progmem_output;
end architecture structural;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity flushing_unit is
port (
clear, clock : in std_logic;
flushing_control : in std_logic;
flushing_output : out std_logic
);
end flushing_unit;
architecture behavioural of flushing_unit is
signal internal_flushing_output : std_logic := '0';
begin
process (clear, clock, flushing_control, internal_flushing_output) is
begin
if (clear = '1') then
internal_flushing_output <= '0';
elsif (clock = '1' and flushing_control = '1') then
internal_flushing_output <= '1';
elsif (clock = '1' and flushing_control = '0') then
internal_flushing_output <= '0';
elsif (clock = '0' and flushing_control = '1') then
internal_flushing_output <= '0';
elsif (clock = '0' and flushing_control = '0') then
internal_flushing_output <= '0';
else
internal_flushing_output <= internal_flushing_output;
end if;
end process;
flushing_output <= internal_flushing_output;
end architecture behavioural;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity forwarding_unit is
port (
reg_file_read_address_0_ID_EXE : in std_logic_vector(4 downto 0);
reg_file_read_address_1_ID_EXE : in std_logic_vector(4 downto 0);
reg_file_write_EX_MEM : in std_logic;
reg_file_write_address_EX_MEM : in std_logic_vector(4 downto 0);
mux_0_sel_EX_MEM : in std_logic_vector(1 downto 0);
reg_file_write_MEM_WB : in std_logic;
reg_file_write_address_MEM_WB : in std_logic_vector(4 downto 0);
mux_0_sel_MEM_WB : in std_logic_vector(1 downto 0);
forward_mux_0_control : out std_logic_vector(2 downto 0);
forward_mux_1_control : out std_logic_vector(2 downto 0)
);
end forwarding_unit;
architecture structural of forwarding_unit is
signal internal_mux_0_control : std_logic_vector(2 downto 0) := "000";
signal internal_mux_1_control : std_logic_vector(2 downto 0) := "000";
begin
forward_0 : process (reg_file_read_address_0_ID_EXE, reg_file_write_EX_MEM, reg_file_write_MEM_WB, reg_file_write_address_EX_MEM, reg_file_write_address_MEM_WB, mux_0_sel_EX_MEM, mux_0_sel_MEM_WB)
begin
if (mux_0_sel_EX_MEM = "00") and (reg_file_write_EX_MEM = '1') and (reg_file_read_address_0_ID_EXE = reg_file_write_address_EX_MEM) and (reg_file_read_address_0_ID_EXE /= "00000") then
internal_mux_0_control <= "001";
elsif (mux_0_sel_EX_MEM = "01") and (reg_file_write_EX_MEM = '1') and (reg_file_read_address_0_ID_EXE = reg_file_write_address_EX_MEM) and (reg_file_read_address_0_ID_EXE /= "00000") then
internal_mux_0_control <= "010";
elsif (mux_0_sel_MEM_WB = "00") and (reg_file_write_MEM_WB = '1') and (reg_file_read_address_0_ID_EXE = reg_file_write_address_MEM_WB) and (reg_file_read_address_0_ID_EXE /= "00000") then
internal_mux_0_control <= "011";
elsif (mux_0_sel_MEM_WB = "01") and (reg_file_write_MEM_WB = '1') and (reg_file_read_address_0_ID_EXE = reg_file_write_address_MEM_WB) and (reg_file_read_address_0_ID_EXE /= "00000") then
internal_mux_0_control <= "100";
else
internal_mux_0_control <= "000";
end if;
end process;
forward_1 : process (reg_file_read_address_1_ID_EXE, reg_file_write_EX_MEM, reg_file_write_MEM_WB, reg_file_write_address_EX_MEM, reg_file_write_address_MEM_WB, mux_0_sel_EX_MEM, mux_0_sel_MEM_WB)
begin
if (mux_0_sel_EX_MEM = "00") and (reg_file_write_EX_MEM = '1') and (reg_file_read_address_1_ID_EXE = reg_file_write_address_EX_MEM) and (reg_file_read_address_1_ID_EXE /= "00000") then
internal_mux_1_control <= "001";
elsif (mux_0_sel_EX_MEM = "01") and (reg_file_write_EX_MEM = '1') and (reg_file_read_address_1_ID_EXE = reg_file_write_address_EX_MEM) and (reg_file_read_address_1_ID_EXE /= "00000") then
internal_mux_1_control <= "010";
elsif (mux_0_sel_MEM_WB = "00") and (reg_file_write_MEM_WB = '1') and (reg_file_read_address_1_ID_EXE = reg_file_write_address_MEM_WB) and (reg_file_read_address_1_ID_EXE /= "00000") then
internal_mux_1_control <= "011";
elsif (mux_0_sel_MEM_WB = "01") and (reg_file_write_MEM_WB = '1') and (reg_file_read_address_1_ID_EXE = reg_file_write_address_MEM_WB) and (reg_file_read_address_1_ID_EXE /= "00000") then
internal_mux_1_control <= "100";
else
internal_mux_1_control <= "000";
end if;
end process;
forward_mux_0_control <= internal_mux_0_control;
forward_mux_1_control <= internal_mux_1_control;
end architecture structural;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity jump_target_unit is
port (
mux_sel : in std_logic;
current_instruction_address : in std_logic_vector(31 downto 0);
regfile_address : in std_logic_vector(31 downto 0);
immediate : in std_logic_vector(31 downto 0);
target_address : out std_logic_vector(31 downto 0)
);
end jump_target_unit;
architecture behavioral of jump_target_unit is
signal mux_output : std_logic_vector (31 downto 0) := X"00000000";
begin
internal_mux : mux_2_1 port map(mux_sel, current_instruction_address, regfile_address, mux_output);
internal_adder : adder port map(mux_output, immediate, target_address);
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity microcontroller is
port (
clock : in std_logic;
reset : in std_logic;
debug_pc_output : out std_logic_vector(31 downto 0);
debug_regfile_x31_output : out std_logic_vector(31 downto 0);
debug_regfile_x1_output : out std_logic_vector(31 downto 0);
debug_regfile_x2_output : out std_logic_vector(31 downto 0);
debug_ALU_output : out std_logic_vector(31 downto 0);
debug_regfile_write : out std_logic;
debug_ALU_input_0 : out std_logic_vector(31 downto 0);
debug_ALU_input_1 : out std_logic_vector(31 downto 0);
debug_reg_file_read_address_0 : out std_logic_vector(4 downto 0);
debug_reg_file_read_address_1 : out std_logic_vector(4 downto 0);
debug_mux0_sel : out std_logic_vector(1 downto 0);
debug_immediate : out std_logic_vector(31 downto 0);
debug_ALU_operation : out std_logic_vector(3 downto 0);
debug_forward_mux_0 : out std_logic_vector(2 downto 0);
debug_forward_mux_1 : out std_logic_vector(2 downto 0);
debug_reg_file_read_address_0_ID_EXE : out std_logic_vector(4 downto 0);
debug_reg_file_write_address_EX_MEM : out std_logic_vector(4 downto 0);
debug_mux0_sel_MEM_WB : out std_logic_vector(1 downto 0);
debug_reg_file_write_MEM_WB : out std_logic;
debug_reg_file_write_address_MEM_WB : out std_logic_vector(4 downto 0);
debug_ALU_output_MEM_WB : out std_logic_vector(31 downto 0);
debug_ALU_output_EX_MEM : out std_logic_vector(31 downto 0);
debug_register_file_output_0 : out std_logic_vector(31 downto 0);
debug_register_file_output_1 : out std_logic_vector(31 downto 0);
debug_register_file_output_0_ID_EX : out std_logic_vector(31 downto 0);
debug_register_file_output_1_ID_EX : out std_logic_vector(31 downto 0);
debug_instruction : out std_logic_vector(31 downto 0)
);
end entity microcontroller;
architecture structural of microcontroller is
signal IF_ID_flush : std_logic;
signal reg_file_read_address_0 : std_logic_vector(4 downto 0);
signal reg_file_read_address_1 : std_logic_vector(4 downto 0);
signal reg_file_write : std_logic;
signal reg_file_write_address : std_logic_vector(4 downto 0);
signal immediate : std_logic_vector(31 downto 0);
signal ALU_operation : std_logic_vector(3 downto 0);
signal ALU_branch : std_logic;
signal ALU_branch_control : std_logic_vector(2 downto 0);
signal JTU_mux_sel : std_logic;
signal data_format : std_logic_vector(2 downto 0);
signal datamem_write : std_logic;
signal jump_flag : std_logic;
signal mux0_sel : std_logic_vector(1 downto 0);
signal mux1_sel : std_logic;
signal instruction : std_logic_vector(31 downto 0);
begin
controller_0 : controller port map(clock, reset, instruction, reg_file_read_address_0, reg_file_read_address_1, reg_file_write, reg_file_write_address, immediate, ALU_operation, ALU_branch, ALU_branch_control, JTU_mux_sel, data_format, datamem_write, jump_flag, mux0_sel, mux1_sel);
datapath_0 : datapath port map(clock, reset, reg_file_read_address_0, reg_file_read_address_1, reg_file_write, reg_file_write_address, immediate, ALU_operation, ALU_branch, ALU_branch_control, JTU_mux_sel, data_format, datamem_write, jump_flag, mux0_sel, mux1_sel, instruction, debug_pc_output, debug_regfile_x31_output, debug_regfile_x1_output, debug_regfile_x2_output, debug_ALU_output, debug_ALU_input_0, debug_ALU_input_1, debug_forward_mux_0, debug_forward_mux_1, debug_reg_file_read_address_0_ID_EXE, debug_reg_file_write_address_EX_MEM, debug_mux0_sel_MEM_WB, debug_reg_file_write_MEM_WB, debug_reg_file_write_address_MEM_WB, debug_ALU_output_MEM_WB, debug_ALU_output_EX_MEM, debug_register_file_output_0, debug_register_file_output_1, debug_register_file_output_0_ID_EX, debug_register_file_output_1_ID_EX, debug_instruction);
debug_regfile_write <= reg_file_write;
debug_reg_file_read_address_0 <= reg_file_read_address_0;
debug_reg_file_read_address_1 <= reg_file_read_address_1;
debug_mux0_sel <= mux0_sel;
debug_immediate <= immediate;
debug_ALU_operation <= ALU_operation;
end architecture structural;

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library ieee;
use ieee.std_logic_1164.all;
entity mux_2_1 is
port (
selection : in std_logic;
input_0, input_1 : in std_logic_vector(31 downto 0);
output_0 : out std_logic_vector(31 downto 0)
);
end mux_2_1;
architecture behavioral of mux_2_1 is
begin
with selection select
output_0 <=
input_0 when '0',
input_1 when '1';
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
entity mux_32_1 is
port (
selection : in std_logic_vector(4 downto 0);
input_0, input_1, input_2, input_3, input_4, input_5, input_6, input_7, input_8, input_9, input_10, input_11, input_12, input_13, input_14, input_15, input_16, input_17,
input_18, input_19, input_20, input_21, input_22, input_23, input_24, input_25, input_26, input_27, input_28, input_29, input_30, input_31 : in std_logic_vector(31 downto 0);
output_0 : out std_logic_vector(31 downto 0)
);
end mux_32_1;
architecture behavioral of mux_32_1 is
begin
with selection select
output_0 <=
input_0 when "00000",
input_1 when "00001",
input_2 when "00010",
input_3 when "00011",
input_4 when "00100",
input_5 when "00101",
input_6 when "00110",
input_7 when "00111",
input_8 when "01000",
input_9 when "01001",
input_10 when "01010",
input_11 when "01011",
input_12 when "01100",
input_13 when "01101",
input_14 when "01110",
input_15 when "01111",
input_16 when "10000",
input_17 when "10001",
input_18 when "10010",
input_19 when "10011",
input_20 when "10100",
input_21 when "10101",
input_22 when "10110",
input_23 when "10111",
input_24 when "11000",
input_25 when "11001",
input_26 when "11010",
input_27 when "11011",
input_28 when "11100",
input_29 when "11101",
input_30 when "11110",
input_31 when "11111";
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_3_1 is
port (
selection : in std_logic_vector(1 downto 0);
input_0, input_1, input_2 : in std_logic_vector(31 downto 0);
output_0 : out std_logic_vector(31 downto 0)
);
end mux_3_1;
architecture behavioral of mux_3_1 is
begin
with selection select
output_0 <=
input_0 when "00",
input_1 when "01",
input_2 when "10",
X"00000000" when others;
end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_5_1 is
port (
selection : in std_logic_vector(2 downto 0);
input_0, input_1, input_2, input_3, input_4 : in std_logic_vector(31 downto 0);
output_0 : out std_logic_vector(31 downto 0)
);
end mux_5_1;
architecture behavioral of mux_5_1 is
begin
with selection select
output_0 <=
input_0 when "000",
input_1 when "001",
input_2 when "010",
input_3 when "011",
input_4 when "100",
X"00000000" when others;
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity progmem_interface is
port (
clock : in std_logic;
byte_address : in std_logic_vector(31 downto 0);
output_data : out std_logic_vector(31 downto 0)
);
end entity progmem_interface;
architecture behavioural of progmem_interface is
signal memory_address : std_logic_vector(31 downto 0) := X"00000000";
begin
address_acquirement : process (byte_address)
begin
memory_address <= std_logic_vector(shift_right(unsigned(byte_address), 2)); --Dividing by 4 since 32 = 4*8
end process;
progmem_0 : progmem port map(memory_address(15 downto 0), clock, output_data);
end architecture behavioural;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity program_counter is
port (
clear, clock : in std_logic;
mux_sel : in std_logic;
address_in_0 : in std_logic_vector(31 downto 0);
address_in_1 : in std_logic_vector(31 downto 0);
next_address : out std_logic_vector(31 downto 0); --THIS OUTPUT IS ONLY REQUIRED WHEN USING REGISTERED INPUT ALTERA MEMORY, SO THE INPUT REG CAN MIRROR THE PC'S INTERNAL REG.
address_out : out std_logic_vector(31 downto 0) --THIS IS THE REAL PC OUTPUT, USE THIS IF YOUR MEMORY DOES NOT HAVE A REGISTER IN ITS INPUT.
);
end program_counter;
architecture behavioral of program_counter is
signal internal_address : std_logic_vector (31 downto 0) := X"00000000";
begin
internal_mux : mux_2_1 port map(mux_sel, address_in_0, address_in_1, internal_address);
internal_register : reg32b port map(internal_address, '1', clock, clear, address_out);
next_address <= internal_address;
end behavioral;

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library ieee;
use ieee.std_logic_1164.all;
entity reg1b is
port (
reg_in : in std_logic;
load, clock, clear : in std_logic;
reg_out : out std_logic
);
end reg1b;
architecture description of reg1b is
signal internal_value : std_logic := '0';
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= '0';
elsif rising_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
entity reg2b is
port (
reg_in : in std_logic_vector(1 downto 0);
load, clock, clear : in std_logic;
reg_out : out std_logic_vector(1 downto 0)
);
end reg2b;
architecture description of reg2b is
signal internal_value : std_logic_vector(1 downto 0) := "00";
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= "00";
elsif rising_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
entity reg32b is
port (
reg_in : in std_logic_vector(31 downto 0);
load, clock, clear : in std_logic;
reg_out : out std_logic_vector(31 downto 0)
);
end reg32b;
architecture description of reg32b is
signal internal_value : std_logic_vector(31 downto 0) := X"00000000";
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= X"00000000";
elsif rising_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
entity reg32b_falling_edge is
port (
reg_in : in std_logic_vector(31 downto 0);
load, clock, clear : in std_logic;
reg_out : out std_logic_vector(31 downto 0)
);
end reg32b_falling_edge;
architecture description of reg32b_falling_edge is
signal internal_value : std_logic_vector(31 downto 0) := X"00000000";
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= X"00000000";
elsif falling_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
entity reg3b is
port (
reg_in : in std_logic_vector(2 downto 0);
load, clock, clear : in std_logic;
reg_out : out std_logic_vector(2 downto 0)
);
end reg3b;
architecture description of reg3b is
signal internal_value : std_logic_vector(2 downto 0) := "000";
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= "000";
elsif rising_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
entity reg4b is
port (
reg_in : in std_logic_vector(3 downto 0);
load, clock, clear : in std_logic;
reg_out : out std_logic_vector(3 downto 0)
);
end reg4b;
architecture description of reg4b is
signal internal_value : std_logic_vector(3 downto 0) := "0000";
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= "0000";
elsif rising_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
entity reg5b is
port (
reg_in : in std_logic_vector(4 downto 0);
load, clock, clear : in std_logic;
reg_out : out std_logic_vector(4 downto 0)
);
end reg5b;
architecture description of reg5b is
signal internal_value : std_logic_vector(4 downto 0) := "00000";
begin
process (clock, clear, load, internal_value)
begin
if (clear = '1') then
internal_value <= "00000";
elsif rising_edge(clock) then
if (load = '1') then
internal_value <= reg_in;
else
internal_value <= internal_value;
end if;
end if;
reg_out <= internal_value;
end process;
end description;

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library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity register_file is
port (
write_data : in std_logic_vector(31 downto 0);
write_address : in std_logic_vector(4 downto 0);
read_address_0 : in std_logic_vector(4 downto 0);
read_address_1 : in std_logic_vector(4 downto 0);
write_control, clock, clear : in std_logic;
output_data_0 : out std_logic_vector(31 downto 0);
output_data_1 : out std_logic_vector(31 downto 0);
debug_x31_output : out std_logic_vector(31 downto 0);
debug_x1_output : out std_logic_vector(31 downto 0);
debug_x2_output : out std_logic_vector(31 downto 0)
);
end entity register_file;
architecture Behavioral of register_file is
signal internal_reg_load : std_logic_vector(31 downto 0) := X"00000000";
signal x0_to_muxes : std_logic_vector(31 downto 0);
signal x1_to_muxes : std_logic_vector(31 downto 0);
signal x2_to_muxes : std_logic_vector(31 downto 0);
signal x3_to_muxes : std_logic_vector(31 downto 0);
signal x4_to_muxes : std_logic_vector(31 downto 0);
signal x5_to_muxes : std_logic_vector(31 downto 0);
signal x6_to_muxes : std_logic_vector(31 downto 0);
signal x7_to_muxes : std_logic_vector(31 downto 0);
signal x8_to_muxes : std_logic_vector(31 downto 0);
signal x9_to_muxes : std_logic_vector(31 downto 0);
signal x10_to_muxes : std_logic_vector(31 downto 0);
signal x11_to_muxes : std_logic_vector(31 downto 0);
signal x12_to_muxes : std_logic_vector(31 downto 0);
signal x13_to_muxes : std_logic_vector(31 downto 0);
signal x14_to_muxes : std_logic_vector(31 downto 0);
signal x15_to_muxes : std_logic_vector(31 downto 0);
signal x16_to_muxes : std_logic_vector(31 downto 0);
signal x17_to_muxes : std_logic_vector(31 downto 0);
signal x18_to_muxes : std_logic_vector(31 downto 0);
signal x19_to_muxes : std_logic_vector(31 downto 0);
signal x20_to_muxes : std_logic_vector(31 downto 0);
signal x21_to_muxes : std_logic_vector(31 downto 0);
signal x22_to_muxes : std_logic_vector(31 downto 0);
signal x23_to_muxes : std_logic_vector(31 downto 0);
signal x24_to_muxes : std_logic_vector(31 downto 0);
signal x25_to_muxes : std_logic_vector(31 downto 0);
signal x26_to_muxes : std_logic_vector(31 downto 0);
signal x27_to_muxes : std_logic_vector(31 downto 0);
signal x28_to_muxes : std_logic_vector(31 downto 0);
signal x29_to_muxes : std_logic_vector(31 downto 0);
signal x30_to_muxes : std_logic_vector(31 downto 0);
signal x31_to_muxes : std_logic_vector(31 downto 0);
begin
register_load_decouple : process (write_address)
begin
if (write_control = '1') then
case write_address is
when "00000" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000000000001";
when "00001" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000000000010";
when "00010" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000000000100";
when "00011" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000000001000";
when "00100" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000000010000";
when "00101" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000000100000";
when "00110" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000001000000";
when "00111" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000010000000";
when "01000" =>
internal_reg_load(31 downto 0) <= "00000000000000000000000100000000";
when "01001" =>
internal_reg_load(31 downto 0) <= "00000000000000000000001000000000";
when "01010" =>
internal_reg_load(31 downto 0) <= "00000000000000000000010000000000";
when "01011" =>
internal_reg_load(31 downto 0) <= "00000000000000000000100000000000";
when "01100" =>
internal_reg_load(31 downto 0) <= "00000000000000000001000000000000";
when "01101" =>
internal_reg_load(31 downto 0) <= "00000000000000000010000000000000";
when "01110" =>
internal_reg_load(31 downto 0) <= "00000000000000000100000000000000";
when "01111" =>
internal_reg_load(31 downto 0) <= "00000000000000001000000000000000";
when "10000" =>
internal_reg_load(31 downto 0) <= "00000000000000010000000000000000";
when "10001" =>
internal_reg_load(31 downto 0) <= "00000000000000100000000000000000";
when "10010" =>
internal_reg_load(31 downto 0) <= "00000000000001000000000000000000";
when "10011" =>
internal_reg_load(31 downto 0) <= "00000000000010000000000000000000";
when "10100" =>
internal_reg_load(31 downto 0) <= "00000000000100000000000000000000";
when "10101" =>
internal_reg_load(31 downto 0) <= "00000000001000000000000000000000";
when "10110" =>
internal_reg_load(31 downto 0) <= "00000000010000000000000000000000";
when "10111" =>
internal_reg_load(31 downto 0) <= "00000000100000000000000000000000";
when "11000" =>
internal_reg_load(31 downto 0) <= "00000001000000000000000000000000";
when "11001" =>
internal_reg_load(31 downto 0) <= "00000010000000000000000000000000";
when "11010" =>
internal_reg_load(31 downto 0) <= "00000100000000000000000000000000";
when "11011" =>
internal_reg_load(31 downto 0) <= "00001000000000000000000000000000";
when "11100" =>
internal_reg_load(31 downto 0) <= "00010000000000000000000000000000";
when "11101" =>
internal_reg_load(31 downto 0) <= "00100000000000000000000000000000";
when "11110" =>
internal_reg_load(31 downto 0) <= "01000000000000000000000000000000";
when "11111" =>
internal_reg_load(31 downto 0) <= "10000000000000000000000000000000";
end case;
else
internal_reg_load(31 downto 0) <= "00000000000000000000000000000000";
end if;
end process;
reg_x0 : reg32b_falling_edge port map(X"00000000", '1', clock, clear, x0_to_muxes);
reg_x1 : reg32b_falling_edge port map(write_data, internal_reg_load(1), clock, clear, x1_to_muxes);
reg_x2 : reg32b_falling_edge port map(write_data, internal_reg_load(2), clock, clear, x2_to_muxes);
reg_x3 : reg32b_falling_edge port map(write_data, internal_reg_load(3), clock, clear, x3_to_muxes);
reg_x4 : reg32b_falling_edge port map(write_data, internal_reg_load(4), clock, clear, x4_to_muxes);
reg_x5 : reg32b_falling_edge port map(write_data, internal_reg_load(5), clock, clear, x5_to_muxes);
reg_x6 : reg32b_falling_edge port map(write_data, internal_reg_load(6), clock, clear, x6_to_muxes);
reg_x7 : reg32b_falling_edge port map(write_data, internal_reg_load(7), clock, clear, x7_to_muxes);
reg_x8 : reg32b_falling_edge port map(write_data, internal_reg_load(8), clock, clear, x8_to_muxes);
reg_x9 : reg32b_falling_edge port map(write_data, internal_reg_load(9), clock, clear, x9_to_muxes);
reg_x10 : reg32b_falling_edge port map(write_data, internal_reg_load(10), clock, clear, x10_to_muxes);
reg_x11 : reg32b_falling_edge port map(write_data, internal_reg_load(11), clock, clear, x11_to_muxes);
reg_x12 : reg32b_falling_edge port map(write_data, internal_reg_load(12), clock, clear, x12_to_muxes);
reg_x13 : reg32b_falling_edge port map(write_data, internal_reg_load(13), clock, clear, x13_to_muxes);
reg_x14 : reg32b_falling_edge port map(write_data, internal_reg_load(14), clock, clear, x14_to_muxes);
reg_x15 : reg32b_falling_edge port map(write_data, internal_reg_load(15), clock, clear, x15_to_muxes);
reg_x16 : reg32b_falling_edge port map(write_data, internal_reg_load(16), clock, clear, x16_to_muxes);
reg_x17 : reg32b_falling_edge port map(write_data, internal_reg_load(17), clock, clear, x17_to_muxes);
reg_x18 : reg32b_falling_edge port map(write_data, internal_reg_load(18), clock, clear, x18_to_muxes);
reg_x19 : reg32b_falling_edge port map(write_data, internal_reg_load(19), clock, clear, x19_to_muxes);
reg_x20 : reg32b_falling_edge port map(write_data, internal_reg_load(20), clock, clear, x20_to_muxes);
reg_x21 : reg32b_falling_edge port map(write_data, internal_reg_load(21), clock, clear, x21_to_muxes);
reg_x22 : reg32b_falling_edge port map(write_data, internal_reg_load(22), clock, clear, x22_to_muxes);
reg_x23 : reg32b_falling_edge port map(write_data, internal_reg_load(23), clock, clear, x23_to_muxes);
reg_x24 : reg32b_falling_edge port map(write_data, internal_reg_load(24), clock, clear, x24_to_muxes);
reg_x25 : reg32b_falling_edge port map(write_data, internal_reg_load(25), clock, clear, x25_to_muxes);
reg_x26 : reg32b_falling_edge port map(write_data, internal_reg_load(26), clock, clear, x26_to_muxes);
reg_x27 : reg32b_falling_edge port map(write_data, internal_reg_load(27), clock, clear, x27_to_muxes);
reg_x28 : reg32b_falling_edge port map(write_data, internal_reg_load(28), clock, clear, x28_to_muxes);
reg_x29 : reg32b_falling_edge port map(write_data, internal_reg_load(29), clock, clear, x29_to_muxes);
reg_x30 : reg32b_falling_edge port map(write_data, internal_reg_load(30), clock, clear, x30_to_muxes);
reg_x31 : reg32b_falling_edge port map(write_data, internal_reg_load(31), clock, clear, x31_to_muxes);
output_1_mux : mux_32_1 port map(
read_address_0, x0_to_muxes, x1_to_muxes, x2_to_muxes, x3_to_muxes, x4_to_muxes, x5_to_muxes, x6_to_muxes, x7_to_muxes,
x8_to_muxes, x9_to_muxes, x10_to_muxes, x11_to_muxes, x12_to_muxes, x13_to_muxes, x14_to_muxes, x15_to_muxes, x16_to_muxes,
x17_to_muxes, x18_to_muxes, x19_to_muxes, x20_to_muxes, x21_to_muxes, x22_to_muxes, x23_to_muxes, x24_to_muxes, x25_to_muxes,
x26_to_muxes, x27_to_muxes, x28_to_muxes, x29_to_muxes, x30_to_muxes, x31_to_muxes, output_data_0);
output_2_mux : mux_32_1 port map(
read_address_1, x0_to_muxes, x1_to_muxes, x2_to_muxes, x3_to_muxes, x4_to_muxes, x5_to_muxes, x6_to_muxes, x7_to_muxes,
x8_to_muxes, x9_to_muxes, x10_to_muxes, x11_to_muxes, x12_to_muxes, x13_to_muxes, x14_to_muxes, x15_to_muxes, x16_to_muxes,
x17_to_muxes, x18_to_muxes, x19_to_muxes, x20_to_muxes, x21_to_muxes, x22_to_muxes, x23_to_muxes, x24_to_muxes, x25_to_muxes,
x26_to_muxes, x27_to_muxes, x28_to_muxes, x29_to_muxes, x30_to_muxes, x31_to_muxes, output_data_1);
debug_x31_output <= x31_to_muxes;
debug_x1_output <= x1_to_muxes;
debug_x2_output <= x2_to_muxes;
end architecture Behavioral;

2068
Quartus/riscv_microcontroller/db/altsyncram_0ed1.tdf Normal file
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36
Quartus/riscv_microcontroller/db/altsyncram_11h1.tdf Normal file
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@ -0,0 +1,36 @@
--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" ENABLE_RUNTIME_MOD="NO" INIT_FILE="progmem.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="OLD_DATA" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources =
SUBDESIGN altsyncram_11h1
(
address_a[7..0] : input;
clock0 : input;
data_a[31..0] : input;
q_a[31..0] : output;
wren_a : input;
)
BEGIN
ASSERT (0)
REPORT "read_during_write_mode_port_a parameter cannot be set to value OLD_DATA for Cyclone II device family"
SEVERITY ERROR;
END;
--ERROR FILE

814
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--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" ENABLE_RUNTIME_MOD="NO" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="OLD_DATA" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_3de1
(
address_a[7..0] : input;
clock0 : input;
data_a[31..0] : input;
q_a[31..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
ram_block1a[31..0].portawe = wren_a;
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE

5692
Quartus/riscv_microcontroller/db/altsyncram_5gs3.tdf Normal file
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Quartus/riscv_microcontroller/db/altsyncram_66s3.tdf Normal file
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@ -0,0 +1,747 @@
--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="progmem.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 NUMWORDS_B=0 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=32 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=8 WIDTHAD_B=1 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_66s3
(
address_a[7..0] : input;
clock0 : input;
q_a[31..0] : output;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE

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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_a4d1
(
address_a[7..0] : input;
address_b[7..0] : input;
clock0 : input;
clock1 : input;
data_a[7..0] : input;
q_b[7..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK1_CORE_CLOCK_ENABLE = "none",
CLK1_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
address_b_wire[7..0] : WIRE;
BEGIN
ram_block1a[7..0].clk0 = clock0;
ram_block1a[7..0].clk1 = clock1;
ram_block1a[7..0].ena0 = wren_a;
ram_block1a[7..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[7..0].portawe = wren_a;
ram_block1a[7..0].portbaddr[] = ( address_b_wire[7..0]);
ram_block1a[7..0].portbre = B"11111111";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
END;
--VALID FILE

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--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" ENABLE_RUNTIME_MOD="NO" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="OLD_DATA" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_b2f1
(
address_a[7..0] : input;
clock0 : input;
data_a[7..0] : input;
q_a[7..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
BEGIN
ram_block1a[7..0].clk0 = clock0;
ram_block1a[7..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[7..0].portare = B"11111111";
ram_block1a[7..0].portawe = wren_a;
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[7..0].portadataout[0..0]);
END;
--VALID FILE

846
Quartus/riscv_microcontroller/db/altsyncram_d9h1.tdf Normal file
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@ -0,0 +1,846 @@
--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" ENABLE_RUNTIME_MOD="NO" INIT_FILE="progmem.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="OLD_DATA" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_d9h1
(
address_a[7..0] : input;
clock0 : input;
data_a[31..0] : input;
q_a[31..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
ram_block1a[31..0].portawe = wren_a;
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE

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--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" ENABLE_RUNTIME_MOD="NO" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="OLD_DATA" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_mbe1
(
address_a[7..0] : input;
clock0 : input;
data_a[7..0] : input;
q_a[7..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
BEGIN
ram_block1a[7..0].clk0 = clock0;
ram_block1a[7..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[7..0].portare = B"11111111";
ram_block1a[7..0].portawe = wren_a;
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[7..0].portadataout[0..0]);
END;
--VALID FILE

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--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV GX" ENABLE_RUNTIME_MOD="NO" INIT_FILE="progmem.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="OLD_DATA" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_oig1
(
address_a[7..0] : input;
clock0 : input;
data_a[31..0] : input;
q_a[31..0] : output;
wren_a : input;
)
VARIABLE
ram_block1a0 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cycloneiv_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "progmem.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_READ_DURING_WRITE_MODE = "old_data",
POWER_UP_UNINITIALIZED = "false",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[7..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[31..0].portare = B"11111111111111111111111111111111";
ram_block1a[31..0].portawe = wren_a;
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
END;
--VALID FILE

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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV GX" LPM_DECODES=8 LPM_WIDTH=3 data eq
--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
--synthesis_resources = lut 8
SUBDESIGN decode_eca
(
data[2..0] : input;
eq[7..0] : output;
)
VARIABLE
data_wire[2..0] : WIRE;
eq_node[7..0] : WIRE;
eq_wire[7..0] : WIRE;
w_anode1046w[3..0] : WIRE;
w_anode1064w[3..0] : WIRE;
w_anode1075w[3..0] : WIRE;
w_anode1086w[3..0] : WIRE;
w_anode1097w[3..0] : WIRE;
w_anode1108w[3..0] : WIRE;
w_anode1119w[3..0] : WIRE;
w_anode1130w[3..0] : WIRE;
BEGIN
data_wire[] = data[];
eq[] = eq_node[];
eq_node[7..0] = eq_wire[7..0];
eq_wire[] = ( w_anode1130w[3..3], w_anode1119w[3..3], w_anode1108w[3..3], w_anode1097w[3..3], w_anode1086w[3..3], w_anode1075w[3..3], w_anode1064w[3..3], w_anode1046w[3..3]);
w_anode1046w[] = ( (w_anode1046w[2..2] & (! data_wire[2..2])), (w_anode1046w[1..1] & (! data_wire[1..1])), (w_anode1046w[0..0] & (! data_wire[0..0])), B"1");
w_anode1064w[] = ( (w_anode1064w[2..2] & (! data_wire[2..2])), (w_anode1064w[1..1] & (! data_wire[1..1])), (w_anode1064w[0..0] & data_wire[0..0]), B"1");
w_anode1075w[] = ( (w_anode1075w[2..2] & (! data_wire[2..2])), (w_anode1075w[1..1] & data_wire[1..1]), (w_anode1075w[0..0] & (! data_wire[0..0])), B"1");
w_anode1086w[] = ( (w_anode1086w[2..2] & (! data_wire[2..2])), (w_anode1086w[1..1] & data_wire[1..1]), (w_anode1086w[0..0] & data_wire[0..0]), B"1");
w_anode1097w[] = ( (w_anode1097w[2..2] & data_wire[2..2]), (w_anode1097w[1..1] & (! data_wire[1..1])), (w_anode1097w[0..0] & (! data_wire[0..0])), B"1");
w_anode1108w[] = ( (w_anode1108w[2..2] & data_wire[2..2]), (w_anode1108w[1..1] & (! data_wire[1..1])), (w_anode1108w[0..0] & data_wire[0..0]), B"1");
w_anode1119w[] = ( (w_anode1119w[2..2] & data_wire[2..2]), (w_anode1119w[1..1] & data_wire[1..1]), (w_anode1119w[0..0] & (! data_wire[0..0])), B"1");
w_anode1130w[] = ( (w_anode1130w[2..2] & data_wire[2..2]), (w_anode1130w[1..1] & data_wire[1..1]), (w_anode1130w[0..0] & data_wire[0..0]), B"1");
END;
--VALID FILE

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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV GX" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
--synthesis_resources = lut 8
SUBDESIGN decode_l0b
(
data[2..0] : input;
enable : input;
eq[7..0] : output;
)
VARIABLE
data_wire[2..0] : WIRE;
enable_wire : WIRE;
eq_node[7..0] : WIRE;
eq_wire[7..0] : WIRE;
w_anode578w[3..0] : WIRE;
w_anode595w[3..0] : WIRE;
w_anode605w[3..0] : WIRE;
w_anode615w[3..0] : WIRE;
w_anode625w[3..0] : WIRE;
w_anode635w[3..0] : WIRE;
w_anode645w[3..0] : WIRE;
w_anode655w[3..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[7..0] = eq_wire[7..0];
eq_wire[] = ( w_anode655w[3..3], w_anode645w[3..3], w_anode635w[3..3], w_anode625w[3..3], w_anode615w[3..3], w_anode605w[3..3], w_anode595w[3..3], w_anode578w[3..3]);
w_anode578w[] = ( (w_anode578w[2..2] & (! data_wire[2..2])), (w_anode578w[1..1] & (! data_wire[1..1])), (w_anode578w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode595w[] = ( (w_anode595w[2..2] & (! data_wire[2..2])), (w_anode595w[1..1] & (! data_wire[1..1])), (w_anode595w[0..0] & data_wire[0..0]), enable_wire);
w_anode605w[] = ( (w_anode605w[2..2] & (! data_wire[2..2])), (w_anode605w[1..1] & data_wire[1..1]), (w_anode605w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode615w[] = ( (w_anode615w[2..2] & (! data_wire[2..2])), (w_anode615w[1..1] & data_wire[1..1]), (w_anode615w[0..0] & data_wire[0..0]), enable_wire);
w_anode625w[] = ( (w_anode625w[2..2] & data_wire[2..2]), (w_anode625w[1..1] & (! data_wire[1..1])), (w_anode625w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode635w[] = ( (w_anode635w[2..2] & data_wire[2..2]), (w_anode635w[1..1] & (! data_wire[1..1])), (w_anode635w[0..0] & data_wire[0..0]), enable_wire);
w_anode645w[] = ( (w_anode645w[2..2] & data_wire[2..2]), (w_anode645w[1..1] & data_wire[1..1]), (w_anode645w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode655w[] = ( (w_anode655w[2..2] & data_wire[2..2]), (w_anode655w[1..1] & data_wire[1..1]), (w_anode655w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE

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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Wed Aug 14 17:21:09 2019

BIN
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ADDRESS_ACLR_A=NONE
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
INIT_FILE=progmem.mif
INTENDED_DEVICE_FAMILY="Cyclone IV GX"
MAXIMUM_DEPTH=8192
NUMWORDS_A=65536
OPERATION_MODE=ROM
OUTDATA_ACLR_A=NONE
OUTDATA_REG_A=UNREGISTERED
WIDTHAD_A=16
WIDTH_A=32
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone IV GX"
address_a
clock0
q_a

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--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
component progmem
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;

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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
-- Quartus Prime generated Memory Initialization File (.mif)
WIDTH=32;
DEPTH=256;
ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;
CONTENT BEGIN
0 : 00000000000000000000000000000000;
1 : 00000000000100000000000100010011;
2 : 00000000001000000000111110110011;
3 : 00000000001000001000000010110011;
4 : 00000000000100000000111110110011;
5 : 00000000000100010000000100110011;
6 : 00000000001000000000111110110011;
7 : 00000000100000000000000001100111;
[8..255] : 00000000000000000000000000000000;
END;

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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV GX}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "progmem.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "progmem.cmp"]

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-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: progmem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY progmem IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END progmem;
ARCHITECTURE SYN OF progmem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "progmem.mif",
intended_device_family => "Cyclone IV GX",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
maximum_depth => 8192,
numwords_a => 65536,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 16,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "8192"
-- Retrieval info: PRIVATE: MIFfilename STRING "progmem.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "progmem.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "8192"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL progmem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 13:04:35 April 24, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "13:04:35 April 24, 2019"
# Revisions
PROJECT_REVISION = "riscv_microcontroller"

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Quartus/riscv_microcontroller/riscv_microcontroller.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 13:04:35 April 24, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# riscv_microcontroller_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY microcontroller
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:04:35 APRIL 24, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS COMMAND_MACRO_MODE -section_id eda_simulation
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do -section_id eda_simulation
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "E:/Documents-bkp/UFRN/TCC - with debug signals/Quartus/riscv_microcontroller/microcontroller.vwf"
set_global_assignment -name MIF_FILE progmem.mif
set_global_assignment -name VHDL_FILE ../../Project/Components/datamem.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_5_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/jump_target_unit.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/flushing_unit.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/adder.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg32b_falling_edge.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/IF_ID_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/forwarding_unit.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg4b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg3b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg2b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg1b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/MEM_WB_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/ID_EX_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/EX_MEM_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/register_file.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg32b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/program_counter.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/progmem_interface.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_32_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_2_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/microcontroller.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/datapath.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/datamem_interface.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/controller.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/ALU.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE microcontroller.vwf
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_3_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg5b.vhd
set_global_assignment -name QIP_FILE progmem.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Quartus/riscv_microcontroller/riscv_microcontroller.qws Normal file
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Quartus/riscv_microcontroller/riscv_microcontroller_assignment_defaults.qdf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 00:01:27 July 15, 2019
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL -value OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY -value "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

23
Quartus/riscv_microcontroller/riscv_microcontroller_nativelink_simulation.rpt Normal file
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@ -0,0 +1,23 @@
Info: Start Nativelink Simulation process
Info: NativeLink has detected VHDL design -- VHDL simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : cycloneivgx
Quartus root : d:/programs/altera/quartus/quartus/bin64/
Quartus sim root : d:/programs/altera/quartus/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : vhdl
Version : 93
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation\modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script d:/programs/altera/quartus/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File riscv_microcontroller_run_msim_rtl_vhdl.do already exists - backing up current file as riscv_microcontroller_run_msim_rtl_vhdl.do.bak3
Info: Spawning ModelSim-Altera Simulation software

564
Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.do Normal file
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@ -0,0 +1,564 @@
vlog -work work E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.vt
vsim -novopt -c -t 1ps -L cycloneiv_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.microcontroller_vlg_vec_tst
onerror {resume}
add wave {microcontroller_vlg_vec_tst/i1/debug_controller_state}
add wave {microcontroller_vlg_vec_tst/i1/debug_controller_state[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_controller_state[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_controller_state[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_pc_output[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x31_output[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x1_output[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_x2_output[0]}
add wave {microcontroller_vlg_vec_tst/i1/clock}
add wave {microcontroller_vlg_vec_tst/i1/reset}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_regfile_write}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_0[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_input_1[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_1}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_1[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_1[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_1[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_1[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_1[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[31]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[30]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[29]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[28]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[27]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[26]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[25]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[24]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[23]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[22]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[21]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[20]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[19]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[18]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[17]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[16]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[15]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[14]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[13]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[12]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[11]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[10]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[9]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[8]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[7]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_immediate[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_mux0_sel}
add wave {microcontroller_vlg_vec_tst/i1/debug_mux0_sel[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_mux0_sel[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_operation}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_operation[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_operation[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_operation[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_operation[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_forward_mux_0}
add wave {microcontroller_vlg_vec_tst/i1/debug_forward_mux_0[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_forward_mux_0[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_forward_mux_1}
add wave {microcontroller_vlg_vec_tst/i1/debug_forward_mux_1[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_forward_mux_1[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_write_address_EX_MEM}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_write_address_EX_MEM[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_write_address_EX_MEM[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_write_address_EX_MEM[2]}
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add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0_ID_EXE}
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add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0_ID_EXE[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0_ID_EXE[2]}
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add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_read_address_0_ID_EXE[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_register_file_read_address_0_from_IF}
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add wave {microcontroller_vlg_vec_tst/i1/debug_register_file_read_address_0_from_IF[3]}
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add wave {microcontroller_vlg_vec_tst/i1/debug_register_file_read_address_0_from_IF[0]}
add wave {microcontroller_vlg_vec_tst/i1/debug_mux0_sel_from_MEM}
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add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_write_address_from_MEM}
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add wave {microcontroller_vlg_vec_tst/i1/debug_reg_file_write_from_MEM}
add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output_from_MEM}
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add wave {microcontroller_vlg_vec_tst/i1/debug_ALU_output_from_EX}
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add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[6]}
add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[5]}
add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[4]}
add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[3]}
add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[2]}
add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[1]}
add wave {microcontroller_vlg_vec_tst/i1/debug_instruction[0]}
run -all

9938
Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.vt Normal file
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324
Quartus/riscv_microcontroller/simulation/modelsim/modelsim.ini Normal file
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@ -0,0 +1,324 @@
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
others = $MODEL_TECH/../modelsim.ini
; Altera Primitive libraries
;
; VHDL Section
;
;
; Verilog Section
;
work = rtl_work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both

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@ -0,0 +1,130 @@
# Reading D:/Programs/Altera/Quartus/modelsim_ase/tcl/vsim/pref.tcl
# do riscv_microcontroller_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\Programs\Altera\Quartus\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\Programs\Altera\Quartus\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
#
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity reg32b_falling_edge
# -- Compiling architecture description of reg32b_falling_edge
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity reg4b
# -- Compiling architecture description of reg4b
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity reg3b
# -- Compiling architecture description of reg3b
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity reg2b
# -- Compiling architecture description of reg2b
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity reg1b
# -- Compiling architecture description of reg1b
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity progmem
# -- Compiling architecture SYN of progmem
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity datamem
# -- Compiling architecture SYN of datamem
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity reg32b
# -- Compiling architecture description of reg32b
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity program_counter
# -- Compiling architecture behavioral of program_counter
# vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity mux_32_1
# -- Compiling architecture behavioral of mux_32_1
# ** Error: E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd(15): (vcom-1339) Selected signal assignment choices cover only 32 out of 59049 cases.
#
# ** Error: E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd(49): VHDL Compiler exiting
# ** Error: D:/Programs/Altera/Quartus/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./riscv_microcontroller_run_msim_rtl_vhdl.do line 17
# D:/Programs/Altera/Quartus/modelsim_ase/win32aloem/vcom failed.
# while executing
# "vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}"
do E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.do
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module microcontroller_vlg_sample_tst
# -- Compiling module microcontroller_vlg_check_tst
# -- Compiling module microcontroller_vlg_vec_tst
#
# Top level modules:
# microcontroller_vlg_vec_tst
# vsim -L cycloneiv_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.microcontroller_vlg_vec_tst
# Loading work.microcontroller_vlg_vec_tst
# ** Error: (vsim-3033) E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.vt(9883): Instantiation of 'microcontroller' failed. The design unit was not found.
#
# Region: /microcontroller_vlg_vec_tst
# Searched libraries:
# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/cycloneiv
# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/altera
# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/altera_mf
# D:/Programs/Altera/Quartus/modelsim_ase/altera/verilog/220model
# D:/Programs/Altera/Quartus/modelsim_ase/altera/vhdl/sgate
# E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/rtl_work
# Loading work.microcontroller_vlg_sample_tst
# Loading work.microcontroller_vlg_check_tst
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO E:\Documents-bkp\UFRN\TCC\Quartus\riscv_microcontroller\simulation\modelsim\microcontroller.vwf.do PAUSED at line 2
vlib tcc
vmap tcc tcc
# Modifying modelsim.ini
vmap -del tcc
# Removing reference to logical library tcc
# Modifying modelsim.ini
vsim rtl_work.microcontroller_vlg_check_tst
# vsim rtl_work.microcontroller_vlg_check_tst
# Loading work.microcontroller_vlg_check_tst
# Load canceled
vsim rtl_work.microcontroller_vlg_check_tst
# vsim rtl_work.microcontroller_vlg_check_tst
# Loading rtl_work.microcontroller_vlg_check_tst

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@ -0,0 +1,27 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=32;
DEPTH=256;
ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;
CONTENT BEGIN
0 : 00000000000100010000000100010011;
1 : 00000000001000000000111110110011;
[2..255] : 00000000000000000000000000000000;
END;

1
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@ -0,0 +1 @@
set tool_name "ModelSim-Altera (Verilog)"

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85528
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3941
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34
Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do Normal file
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transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_2_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ALU.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_3_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg5b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/IF_ID_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/forwarding_unit.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/MEM_WB_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ID_EX_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/EX_MEM_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/register_file.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/progmem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datapath.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datamem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/controller.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/microcontroller.vhd}
do "E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do"

33
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transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_2_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ALU.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_3_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg5b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/IF_ID_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/forwarding_unit.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/MEM_WB_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ID_EX_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/EX_MEM_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/progmem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/microcontroller.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datapath.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datamem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/controller.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/register_file.vhd}

33
Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do.bak1 Normal file
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@ -0,0 +1,33 @@
transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_2_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ALU.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_3_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg5b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/IF_ID_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/forwarding_unit.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/MEM_WB_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ID_EX_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/EX_MEM_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/register_file.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/progmem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/microcontroller.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datapath.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datamem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/controller.vhd}

33
Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do.bak2 Normal file
View file

@ -0,0 +1,33 @@
transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_2_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ALU.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_3_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg5b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/IF_ID_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/forwarding_unit.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/MEM_WB_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ID_EX_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/EX_MEM_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/register_file.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/progmem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/microcontroller.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datapath.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datamem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/controller.vhd}

34
Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do.bak3 Normal file
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@ -0,0 +1,34 @@
transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b_falling_edge.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg4b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg3b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg2b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg1b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/progmem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Quartus/Datapath/datamem.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg32b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/program_counter.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_32_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_2_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ALU.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/mux_3_1.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/reg5b.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/IF_ID_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/forwarding_unit.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/MEM_WB_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/ID_EX_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/EX_MEM_DIV.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/register_file.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/progmem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datapath.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/datamem_interface.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/controller.vhd}
vcom -93 -work work {E:/Documents-bkp/UFRN/TCC/Project/Components/microcontroller.vhd}
do "E:/Documents-bkp/UFRN/TCC/Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do"

70031
Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_v.sdo Normal file
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File diff suppressed because it is too large Load diff

398
Quartus/riscv_microcontroller/simulation/modelsim/rtl_work/_info Normal file
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@ -0,0 +1,398 @@
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m255
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library verilog;
use verilog.vl_types.all;
entity microcontroller_vlg_check_tst is
port(
debug_ALU_input_0: in vl_logic_vector(31 downto 0);
debug_ALU_input_1: in vl_logic_vector(31 downto 0);
debug_ALU_operation: in vl_logic_vector(3 downto 0);
debug_ALU_output: in vl_logic_vector(31 downto 0);
debug_ALU_output_from_EX: in vl_logic_vector(31 downto 0);
debug_ALU_output_from_MEM: in vl_logic_vector(31 downto 0);
debug_controller_state: in vl_logic_vector(2 downto 0);
debug_forward_mux_0: in vl_logic_vector(1 downto 0);
debug_forward_mux_1: in vl_logic_vector(1 downto 0);
debug_immediate : in vl_logic_vector(31 downto 0);
debug_instruction: in vl_logic_vector(31 downto 0);
debug_mux0_sel : in vl_logic_vector(1 downto 0);
debug_mux0_sel_from_MEM: in vl_logic_vector(1 downto 0);
debug_PC_operation: in vl_logic_vector(2 downto 0);
debug_pc_output : in vl_logic_vector(31 downto 0);
debug_reg_file_read_address_0: in vl_logic_vector(4 downto 0);
debug_reg_file_read_address_0_ID_EXE: in vl_logic_vector(4 downto 0);
debug_reg_file_read_address_1: in vl_logic_vector(4 downto 0);
debug_reg_file_write_address_EX_MEM: in vl_logic_vector(4 downto 0);
debug_reg_file_write_address_from_MEM: in vl_logic_vector(4 downto 0);
debug_reg_file_write_from_MEM: in vl_logic;
debug_regfile_write: in vl_logic;
debug_regfile_x1_output: in vl_logic_vector(31 downto 0);
debug_regfile_x2_output: in vl_logic_vector(31 downto 0);
debug_regfile_x31_output: in vl_logic_vector(31 downto 0);
debug_register_file_output_0: in vl_logic_vector(31 downto 0);
debug_register_file_output_0_from_ID: in vl_logic_vector(31 downto 0);
debug_register_file_output_1: in vl_logic_vector(31 downto 0);
debug_register_file_output_1_from_ID: in vl_logic_vector(31 downto 0);
sampler_rx : in vl_logic
);
end microcontroller_vlg_check_tst;

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library verilog;
use verilog.vl_types.all;
entity microcontroller_vlg_sample_tst is
port(
clock : in vl_logic;
reset : in vl_logic;
sampler_tx : out vl_logic
);
end microcontroller_vlg_sample_tst;

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