tinebp
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fb4527fe95
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cache repl reset
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2025-01-21 01:06:22 -08:00 |
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tinebp
|
87297e0eca
|
bug fixes
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2025-01-14 02:21:17 -08:00 |
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tinebp
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347889c504
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minor updates
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2025-01-11 03:24:06 -08:00 |
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tinebp
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704f525fd6
|
memory mem_coalescer miss perf counter
RTL perf counters refactoring
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2024-12-26 08:00:36 -08:00 |
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tinebp
|
066ab105eb
|
multiports fixes
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2024-12-17 16:23:08 -08:00 |
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tinebp
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a98d2e24e5
|
rtlsim multibanks
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2024-12-16 22:10:57 -08:00 |
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tinebp
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461f2cbbc9
|
Intel Opae AFU support for multiport
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2024-12-13 21:20:38 -08:00 |
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tinebp
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7975a5a38c
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fixed AXI adapter
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2024-12-12 20:52:45 -08:00 |
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tinebp
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f635d71ba4
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minor fix
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2024-12-11 10:31:03 -08:00 |
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tinebp
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70ade222b1
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multiport
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2024-12-10 23:25:05 -08:00 |
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tinebp
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dfc7b6178c
|
cleanup old cache test
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2024-11-13 20:56:06 -08:00 |
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tinebp
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bffc6d9610
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enabling Vivado's asynchronous bram suppot via direct netlist transformation
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2024-11-13 16:20:25 -08:00 |
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Blaise Tine
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8b172d07ec
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revert xilinx's asynchronous bram workaround
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2024-10-24 01:44:55 -07:00 |
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Blaise Tine
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e7d09feb4a
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decode => demux
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2024-10-23 13:06:45 -07:00 |
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Blaise Tine
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1fa4603fa2
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disable sformatf during synthesis
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2024-10-23 01:14:19 -07:00 |
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Blaise Tine
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1e4f0fa0bd
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minor update
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2024-10-20 21:42:02 -07:00 |
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Blaise Tine
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22c3828bf5
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minor update
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2024-10-20 21:12:49 -07:00 |
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Blaise Tine
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acc1e3dfd8
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minor update
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2024-10-20 20:07:34 -07:00 |
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Blaise Tine
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0f380a3d78
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minor update
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2024-10-20 07:49:27 -07:00 |
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Blaise Tine
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9373e21950
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minor update
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2024-10-20 07:32:32 -07:00 |
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Blaise Tine
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2bd22253eb
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minor update
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2024-10-19 22:14:38 -07:00 |
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Blaise Tine
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4206ffdb80
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minor update
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2024-10-19 21:39:34 -07:00 |
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Blaise Tine
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b6bd6467ef
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cache hit timing optimization
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2024-10-19 20:04:51 -07:00 |
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Blaise Tine
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8f29ad58ae
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block ram redesign to support synthesizable write-first mode
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2024-10-18 23:54:20 -07:00 |
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Blaise Tine
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6b1091e08f
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minor update
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2024-10-17 14:07:22 -07:00 |
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Blaise Tine
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91fee5da11
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minor update
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2024-10-17 11:25:17 -07:00 |
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Blaise Tine
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077b682d7d
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minor update
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2024-10-17 04:58:29 -07:00 |
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Blaise Tine
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5971158f43
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minor update
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2024-10-16 20:22:42 -07:00 |
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Blaise Tine
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a7ba377581
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minor update
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2024-10-16 18:04:11 -07:00 |
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Blaise Tine
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f695e4d754
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minor update
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2024-10-15 14:59:31 -07:00 |
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Blaise Tine
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645befdce6
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minor update
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2024-10-15 11:23:29 -07:00 |
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Blaise Tine
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e62b638d88
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minor update
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2024-10-15 10:36:05 -07:00 |
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Blaise Tine
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1d5e4f63dd
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minor update
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2024-10-15 03:24:02 -07:00 |
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Blaise Tine
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03a1e25828
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adding cache replacement policy
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2024-10-15 00:28:09 -07:00 |
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Blaise Tine
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37757fab8f
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fixed fifo_queue support for BRAM
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2024-10-14 15:48:49 -07:00 |
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Blaise Tine
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2a2fc2ae39
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minor update
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2024-10-13 23:25:41 -07:00 |
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Blaise Tine
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f63233334e
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minor update
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2024-10-13 16:22:59 -07:00 |
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Blaise Tine
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1d626588ef
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minor update
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2024-10-13 11:49:12 -07:00 |
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Blaise Tine
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37f4d05393
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minor update
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2024-10-13 10:44:04 -07:00 |
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Blaise Tine
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28bf27e951
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rtl cache redesign to support xilinx bram types
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2024-10-13 03:40:45 -07:00 |
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Blaise Tine
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a5381fd788
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async bram optimization
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2024-10-09 04:14:15 -07:00 |
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Blaise Tine
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ee96d4334b
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VX_onehot_encoder update
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2024-10-08 23:01:01 -07:00 |
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Blaise Tine
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c91f9684fc
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minor update
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2024-10-05 18:35:26 -07:00 |
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Blaise Tine
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07ce16e75c
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minor update
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2024-10-05 17:42:26 -07:00 |
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Blaise Tine
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2eeb2ac532
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fixed memory flags propagation through the cache hierarchy
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2024-10-05 13:46:10 -07:00 |
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Blaise Tine
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1deb13c469
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minor update
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2024-09-30 03:36:00 -07:00 |
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Blaise Tine
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29ea3041c4
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build fix
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2024-09-23 03:52:03 -07:00 |
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Blaise Tine
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a37309c6b0
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xrtsim implementation
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2024-09-19 04:24:20 -07:00 |
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263893eb7c
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minor update
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2024-09-13 00:03:08 -07:00 |
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Blaise Tine
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6cf0d9f7b4
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fixed generate labels lint warnings to improve hardware debugging
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2024-09-12 20:00:50 -07:00 |
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