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Code Issues Projects Releases Packages Wiki Activity Actions 7
2094 commits 16 branches 13 tags 288 MiB
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396 commits

Author SHA1 Message Date
Florian Zaruba
622a09779a 🎨 Flatten tb submodule 2018-08-01 01:39:01 +02:00
Florian Zaruba
e423793858 🎨 Remove axi2per 2018-08-01 01:17:41 +02:00
Florian Zaruba
3452d79fc3 Set default trap vector to boot_adr + 'h40 2018-07-31 01:14:53 +02:00
Florian Zaruba
b37d9c1c5e 🐛 Fix bug which led to an unreachable program buffer 2018-07-27 23:56:53 +02:00
Florian Zaruba
075561353f 🐛 Fix IDCODE enumeration error 2018-07-26 02:35:43 +02:00
Florian Zaruba
6cd0486dcd
Merge branch 'riscv-compliant-debug' of github.com:pulp-platform/ariane into riscv-compliant-debug 2018-07-25 16:25:59 -07:00
Florian Zaruba
6c54fc5b28 Minor syntax fixes, DPI build clean-up 2018-07-26 01:23:40 +02:00
Florian Zaruba
6e5fc3fef2
Enable tracing and add openocd debug conf 2018-07-25 11:59:50 -07:00
Florian Zaruba
9c1b32e1c9
De-activate trace feature for now 2018-07-25 00:18:13 -07:00
Florian Zaruba
09981eabc0
Small fixes and verilator update 2018-07-24 22:17:12 -07:00
Florian Zaruba
f091dbce57
💚 Fix CI problem pulling riscv-fesvr 2018-07-24 20:59:26 -07:00
Florian Zaruba
3ec61a67cc
Change build dir, adapt README 2018-07-24 18:24:45 -07:00
Florian Zaruba
1a13c07a8f
💚 Use travis verilator 2018-07-24 17:41:04 -07:00
Florian Zaruba
2702259c5d
Update to upstream fesvr, run CI in parallel 2018-07-24 17:04:13 -07:00
Florian Zaruba
235ff61e6f Fix argument parsing for Modelsim 2018-07-19 23:26:01 +02:00
Florian Zaruba
dadb186c9e Remove timeunit definitions 2018-07-17 01:04:27 +02:00
Florian Zaruba
bc8cff782f Fix Modelsim flow 2018-07-16 23:53:18 +02:00
Florian Zaruba
04902ce01e
🚧 Remove dm_ctrl and move logic to dm_memory 2018-07-12 17:36:14 -07:00
Florian Zaruba
54bbced94f
✨ Add debug hart ctrl memory interface 2018-07-11 16:25:49 -07:00
Florian Zaruba
f501291661
✨ Add first-stage bootloader 2018-07-10 14:25:35 -07:00
Florian Zaruba
1f7244e1a0
🚧 Instantiate Hart Ctrl 2018-07-10 11:35:12 -07:00
Florian Zaruba
eb95474ace
🐛 Minor fixes to hart enumeration logic 2018-07-10 10:29:47 -07:00
Florian Zaruba
527e944577
🚧 Verilator debug integration 2018-07-10 09:20:07 -07:00
Florian Zaruba
b79a8b6e9a
🚧 Add missing debug CSRs 2018-07-02 16:03:21 -07:00
Florian Zaruba
cf431ee491
🚧 Add debug CSRs to DM 2018-06-30 18:51:23 -07:00
Florian Zaruba
e942c2052b
♻️ Re-factor packages and add debug pkg 2018-06-30 16:51:54 -07:00
Florian Zaruba
9d1218529e
Make icache bypass-able 2018-06-30 19:27:40 +02:00
Stefan Mach
6158c5a14c 🐛 Fix misc. FPU bugs and bump FP dependencies 2018-04-20 16:04:56 +02:00
Florian Zaruba
d8552d5ecd Pump tb version 2018-04-18 15:11:14 +02:00
Jonathan Richard Robert Kimmitt
3acc3e0d67 Add travis pre-check script and remove spurious spaces from Makefile 2018-04-18 15:11:14 +02:00
Jonathan Richard Robert Kimmitt
1ce21e961d Add placeholders for PMP CSRs for memory protection. 2018-04-18 15:11:14 +02:00
Stefan Mach
12bd35ce7d 🚧 Working on FPU integration to Ariane 2018-04-18 15:10:55 +02:00
Florian Zaruba
259e089ae3 🚧 Parameterize register file (FPU preparation) 2018-04-18 14:53:47 +02:00
Florian Zaruba
7b0a436d70
Pump tb version 2018-04-09 15:33:40 +02:00
Florian Zaruba
bd9e852596
Merge branch 'master' into ariane_next 2018-04-09 15:18:45 +02:00
Florian Zaruba
62fc4bd816
Pump submodules, cherry-pick TLB clean-up 2018-04-09 15:11:15 +02:00
Jonathan Richard Robert Kimmitt
7f95cbb0fc Add travis pre-check script and remove spurious spaces from Makefile 2018-03-21 16:58:53 +00:00
Jonathan Richard Robert Kimmitt
e20dd9de2a Add placeholders for PMP CSRs for memory protection. 2018-03-21 15:19:37 +00:00
Florian Zaruba
a712ad8afc
Remove potential collisions on regfile 2018-03-16 13:18:15 +01:00
Florian Zaruba
594d4687e9
Merge branch 'new-frontend' into ariane_next 2018-03-14 14:35:49 +01:00
raulbehl
82a9a345e5 🎨 Fixes for #16 
- Updated simc target to automatically run the test by adding
    run -a in the do command
 2018-03-08 00:33:13 +05:30
Rahul Behl
381b90476f
Update Makefile 
- Added back the elfdpi.h creation as it is required by build-dpi target
 2018-03-04 19:35:53 +05:30
raulbehl
11afcad9c2 Fix for #10 
- Added build-dpi target in Make to compile DPI C-code using gcc
  - Updated the vsim commands in the Makefile to include the newly
    generated DPI library
  - Updated the vsim command with the "-64" switch as we are always
    using this switch with vlog
 2018-03-04 17:09:45 +05:30
Florian Zaruba
6c66ea19ae VM based RISC-V tests are passing 2018-02-16 12:39:44 +01:00
Florian Zaruba
ec5ef97d55 Implement RVC without RVI perf impact 2018-02-15 18:23:00 +01:00
Florian Zaruba
c57ce142e7 Update BHT and BTB separately 
Dhrystone > 1.7 DMIPS
 2018-02-14 17:31:02 +01:00
Florian Zaruba
74d99521df Start validating rv64ui-p-* tests 2018-02-13 17:07:23 +01:00
Florian Zaruba
4f73473b1b Fix issue with next PC calculation 2018-02-12 17:39:11 +01:00
Florian Zaruba
140ed0cadc
Add instruction scanner 2018-02-08 23:10:38 +01:00
Florian Zaruba
30b1e5f464
Add option parsing to verilator environment 2018-02-01 18:52:03 +01:00