JeanRochCoulon
58d490b461
Update PMP entry number from 16 to 64 ( #2343 )
2024-07-10 09:54:16 +00:00
LQUA
f44655809f
Add CV64A6_MMU core in user manual ( #2324 )
2024-07-09 16:49:31 +02:00
André Sintzoff
51114ee0a1
machine.adoc: add missing table ( #2331 )
...
For CVA6, add table:
Encoding of A field in PMP configuration registers
2024-07-05 23:49:20 +02:00
André Sintzoff
0bd8b8693a
update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 ( #2323 )
...
since last riscv-isa-manual update (CVA6 commit 105d3601b
2024-07-05 12:06:16 +02:00
LQUA
66caecdfe6
Add RISCV documentation for cv64a6_mmu ( #2315 )
2024-07-03 17:24:07 +02:00
André Sintzoff
89568b0c10
doc: clarify mtval register description when not enabled ( #2271 )
2024-06-19 13:00:33 +02:00
AngelaGonzalezMarino
db088159eb
Mmu design document ( #2117 )
2024-06-17 09:23:44 +02:00
slgth
802066bfd3
docs: move riscv-isa-manual outside of cv32a65x documentation ( #2264 )
2024-06-16 23:20:41 +02:00
JeanRochCoulon
7e8e2c931f
Fix CSR chapter insertion and rename Design Doc names (remove "for cv32a65x") ( #2262 )
2024-06-14 15:39:22 +02:00
André Sintzoff
105d3601b6
update riscv-isa-manual to riscv-isa-release-c8c8075-2024-06-12 ( #2253 )
2024-06-13 16:45:04 +02:00
slgth
b1850a8cb7
docs: fix spec_builder.py ( #2249 )
2024-06-12 20:07:22 +02:00
André Sintzoff
361b17e7b0
cv32a65x doc: fix RISC-V unpriv pdf generation
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issue introduced in 718c4e23
2024-06-12 11:32:36 +02:00
André Sintzoff
d5b7cc77ff
cv32a65x doc: split unpriv and priv HTML pages
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Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2024-06-12 11:18:31 +02:00
slgth
f57a6c0106
Move CV32A65X documentation into its own chapter ( #2236 )
2024-06-11 18:01:25 +02:00
JeanRochCoulon
91871d97f3
Update functionality.rst ( #2235 )
2024-06-11 12:31:52 +02:00
JeanRochCoulon
9d02734bd1
Fix PMPCFG number (from 8 to 4, from which 2 are read-only zero) ( #2232 )
2024-06-11 11:15:27 +02:00
André Sintzoff
ba6262a65c
add Unprivileged RISC-V ISA for CV32A65X doc ( #2186 )
2024-06-03 12:13:16 +02:00
André Sintzoff
227a3f4ff9
doc cv32a65x: update xPELP fields in mstatus ( #2177 )
2024-05-31 12:48:12 +02:00
André Sintzoff
718c4e23b3
update riscv-isa-manual to riscv-isa-release-1bec7d3-2024-05-28 ( #2169 )
2024-05-30 17:54:30 +02:00
JeanRochCoulon
b6495684ba
Insert CSR generated from riscv-config ( #2162 )
2024-05-29 09:37:31 +02:00
AngelaGonzalezMarino
f8914b9237
Mmu user manual ( #2118 )
2024-05-28 17:45:22 +02:00
JeanRochCoulon
f0adb7680b
Update the specification following the last commits (RVF, SUPERSCALAR,...) ( #2155 )
2024-05-27 18:02:40 +02:00
AEzzejjari
f0deb6104c
axi Specification: Modify the AXI memory interface specification ( #1960 )
2024-05-27 11:52:27 +02:00
JeanRochCoulon
f4109564fd
Update PMA description ( #2148 )
2024-05-23 14:26:22 +02:00
JeanRochCoulon
3d501bb485
Add SPP, SIE, SPIE, MXR and SUM description when S-mode is not implemented. ( #2147 )
2024-05-23 11:25:29 +02:00
André Sintzoff
c52fd2b2c9
Provide RISC-V ISA priv in ReadTheDocs ( #2093 )
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* Provide RISC-V ISA for CV32A65X
* Reorder specifications in ReadTheDocs
2024-05-02 15:20:09 +02:00
JeanRochCoulon
f57efabd6b
doc priv: tailor machine.adoc for CV32A65X ( #2092 )
2024-05-02 10:28:23 +00:00
André Sintzoff
ecee022457
doc priv: tailor RISC-V privilege spec for CV32A65X ( #2078 )
2024-04-30 10:30:41 +02:00
JeanRochCoulon
e1d61182b7
Generate the cv32a65x riscv specification out of the box ( #2054 )
2024-04-22 15:34:21 +02:00
JeanRochCoulon
9a36bf2c3d
define riscv-isa-manual as submodule ( #2052 )
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* remove riscv-isa-manual vendor
* Define riscv-isa-manual as submodule
2024-04-17 12:45:43 +00:00
Côme
f886713754
User config generator becomes a Python tool to work with configs ( #2003 )
2024-04-04 15:56:29 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
JeanRochCoulon
8d6c1f709f
Modify the variable order inside the cva6_user_cfg_t ( #1971 )
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Modify the variable order inside the cva6_user_cfg_t to gather extension params together and micro-architecture params together
2024-03-28 15:19:49 +01:00
JeanRochCoulon
64273ca4af
update Design Doc after bumping H extension ( #1968 )
2024-03-28 09:32:59 +01:00
JeanRochCoulon
c76b29a887
Update after parametrization changes ( #1943 )
2024-03-19 11:09:46 +01:00
Rohan Arshid
b8ca8588cf
Updated Zcmp extension user guide and specification document ( #1930 )
2024-03-15 18:33:01 +01:00
Rohan Arshid
94f6528e1f
[Docs] Add Zcmp Instructions in CVA6 user guide and requirement specifications ( #1927 )
2024-03-13 22:52:44 +01:00
JeanRochCoulon
57f062bd85
Add Caches submodule description in Design Doc ( #1923 )
2024-03-12 17:40:05 +01:00
JeanRochCoulon
378144ddc4
03 doc is deprecated ( #1922 )
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GitHub Issues report 03 doc limitations. As it is not the main design document, we would like to notify that it is deprecated.
2024-03-12 16:36:27 +00:00
JeanRochCoulon
301f18a5f4
Improve FRONTEND description ( #1914 )
2024-03-11 12:52:35 +01:00
JeanRochCoulon
b3ae6e9362
Revert MMU ( #1890 )
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* Revert "fix vcs simulation errors regarding hypervisor extension code (#1889 )"
This reverts commit 5ff5f164fb#1881 )"
This reverts commit 6a5863e71a#1876 )"
This reverts commit 9fb5db2555
2024-03-05 16:44:40 +01:00
AngelaGonzalezMarino
6a5863e71a
Mmu user manual ( #1881 )
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* user manual update mmu v0
* Include information for hypervisor extension use. Fix issue in satp mode bits.
* Remove old text
2024-03-05 13:50:45 +01:00
JeanRochCoulon
483ef90127
Update frontend module description ( #1882 )
2024-03-04 23:18:27 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document ( #1865 )
2024-02-23 23:09:11 +01:00
JeanRochCoulon
b4c287a18e
Design Document, add ID_STAGE description ( #1832 )
2024-02-16 16:17:46 +01:00
JeanRochCoulon
0f2b137984
Populate instruction chapter in CV32A65X Design Document ( #1820 )
2024-02-12 09:58:02 +01:00
Jérôme Quévremont
ef3bb06fbf
Adding configuration-specific CSR doc ( #1766 )
2024-02-09 13:39:48 +01:00
JeanRochCoulon
3f8649ec7e
Table builder for specification ( #1814 )
2024-02-08 10:54:47 +01:00
JeanRochCoulon
9d0c700f42
port_builder generates the table of ports ( #1805 )
2024-02-06 12:06:13 +01:00
André Sintzoff
dc634c61de
doc: update MVENDORID CSR value ( fix #1735 ) ( #1753 )
2024-01-10 11:30:48 +01:00
