Côme
43edcd467e
document issue stage ( #2598 )
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* Fill docs/design/design-manual/source/cva6_issue_stage.adoc
* Add variables to docs/design/design-manual/source/design.adoc
* Update port doc comments in core/issue_stage.sv, core/issue_read_operands.sv and core/scoreboard.sv
2024-11-12 20:28:25 +01:00
Côme
4619a67fc6
expand glob port maps ( #2585 )
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bender-up-to-date / bender-up-to-date (push) Has been cancelled
ci / build-riscv-tests (push) Has been cancelled
ci / execute-riscv64-tests (push) Has been cancelled
ci / execute-riscv32-tests (push) Has been cancelled
Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv.
Also reorders port maps to keep the same order as port declarations.
2024-11-07 16:51:46 +01:00
jzthales
6ccd8d8bfa
Refactor forwarding in issue_stage module ( #2519 )
2024-10-01 06:13:30 +02:00
André Sintzoff
af4e3744d4
spyglass: remove useless assignments ( #2439 )
2024-08-12 15:06:39 +02:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 ( #2340 )
2024-07-12 10:53:18 +02:00
Côme
5fcc39dbee
remove round interval ( #2353 )
2024-07-11 17:35:03 +02:00
Côme
4df49a6b0f
superscalar: make SuperscalarEn a CVA6Cfg attribute ( #2322 )
2024-07-05 14:09:48 +02:00
Côme
96ae8ed223
superscalar: allow speculative instructions ( #2278 )
2024-06-20 15:55:56 +02:00
Côme
eac60af1a9
superscalar: add a second issue port ( #2209 )
2024-06-09 20:47:09 +02:00
Côme
261e5d3192
superscalar: add issue port to scoreboard ( #2081 )
2024-04-26 16:04:04 +02:00
Côme
779927485d
superscalar: duplicate decode stage ( #2077 )
2024-04-26 12:09:42 +02:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
987c645bb7
Parametrization step 3 ( #1935 )
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This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document ( #1865 )
2024-02-23 23:09:11 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
AEzzejjari
738d53af1c
Code coverage: condition RTL With parameters ( #1703 )
2023-12-13 07:52:47 +01:00
André Sintzoff
c51819dcbd
verible-verilog-format: apply it on core directory ( #1668 )
...
using verible-v0.0-3430-g060bde0f/bin/verible-verilog-format
with default configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-12-04 11:16:35 +00:00
Fatima Saleem
b4e5c7fa6a
removing lint warnings.. ( #1571 )
2023-11-20 10:21:04 +01:00
AEzzejjari
1faaec09bc
Code_coverage: condition RTL with the debug parameter ( #1582 )
2023-10-31 17:35:59 +01:00
Fatima Saleem
49a4b5b4ff
resolving lint warnings... ( #1529 )
2023-10-20 15:01:42 +02:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
AEzzejjari
b952b0d7c3
Code_coverage: Add conditions for the FPU ( #1442 )
2023-09-19 18:24:40 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter ( #1320 )
...
* Variane as CVA6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix FPGA build
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix tipo in cva6.sv
* fix lint warnings
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix is_*_fpr functions
* remove blank lines
* set IsRVFI out of CVA6Cfg
* define config_pkg
* Fix ariane_pkg comments
* Fix Lint from André's feedbacks
* Fix parameter transmission
* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv
* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
2023-08-22 14:04:06 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
Fatima Saleem
018dbc4210
Resolved Lint WIDTHTRUNC warnings(1/2) ( #1297 )
2023-07-06 11:41:25 +02:00
JeanRochCoulon
5284f828e4
declare cva6_cfg_t to pass the configuration through the hierarchy ( #1287 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-07-01 17:24:21 +02:00
Zbigniew Chamski
a0893bce2b
Enable assertions in Verilator after migrating to Verilator v5. ( #1185 )
2023-04-19 09:35:40 +02:00
JeanRochCoulon
710da10297
Remove RVFI_TRACE/RVFI_MEM ifdef verilog directive ( #1141 )
...
To allow to remove optionally ports, ifdef directive are kept in cva6_config package.
2023-04-11 07:49:59 +02:00
JeanRochCoulon
0fa60bd593
Fix popcount to be able to configure CVA6 with COMMIT_PORT=1 ( #1068 )
2023-02-15 22:15:44 +01:00
JeanRochCoulon
665d910686
Fix RVFI mem_wdata assignment ( #1055 )
2023-02-09 14:34:29 +01:00
JeanRochCoulon
9109ff07f6
Cvvdev/dev/rvfi ( #959 )
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* Add load and store information to RVFI
* Add rs1 and rs2 information to RVFI
* Condition rvfi mem and rs1/rs2 information generation by RVFI_MEM
This add-on is requested by ISACOV and test termination.
2022-09-21 13:00:59 +02:00
Gianmarco Ottavi
5c0dc1971f
Fixed issue counter in order to leverage the full scoreboad length ( #802 )
...
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2022-01-24 19:48:17 +01:00
Gchauvon
e197b445fc
Add cv-x-interface ( #780 )
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* Add top hierarchy modification and rs3 for general purpose register file
* CVA6 core modifications to enable CoreV-eXtension-Interface feature
* Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6
* CoreV-eXtension-Interface available for FPGA
* Add work directories to gitignore
* Flist: fix cvxif files
* CVXIF: Modification and bugfix for cvxif feature
* CVXIF: simplify destination register feature
* Make 3rd read port on regfile configurable
* example_copro: use fifo_v3 instead of stream_fifo
* Makefile: compilation copro using defines
* ariane_pkg,riscv_pkg: add parameter to en/disable cvxif
* cva6.sv, ariane.sv: add hierarchy between ariane and cva6
* Clean Up code and typo
* CVXIF: moved combinatorial part to cvxif_fu module in ex_stage
* instr_decoder: rename instr predecoder and package
* Clean Up code and typo
* cvxif modification to follow style guideline
* issue_read_operands.sv: fix always_ff block for cvxif functionnal uni
2021-12-22 12:31:56 +01:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
...
* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
