AngelaGonzalezMarino
6e0cf8d730
Altera fpga update ( #2790 )
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Update Altera APU design to support linux in both 32 and 64 bits
* Move JTAG UART inside peripherals to properly connect the interruput request to PLIC
* Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version
* Update UART read and write operation in bootrom to allow keyboard interrupt
2025-02-25 22:12:55 +01:00
AngelaGonzalezMarino
eab88770ec
Altera flow support ( #2649 )
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Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap
2025-01-07 23:45:49 +01:00
AngelaGonzalezMarino
f7eb9c1e7b
Altera apu agilex7 ( #2647 )
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This PR is adding the APU design adapted to Altera Agilex7 FPGA.
It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.
2024-12-04 15:54:41 +01:00
Gregor Haas
c92245b20b
Implement simple uart-based updater for the bootrom ( #2267 )
2024-06-19 11:24:01 +02:00
xiaoweish
c93587b1f9
Update UART submodule to version 0.2.1 and Use SV UART in vcs-testharness ( #2196 )
2024-06-17 09:24:18 +02:00
AngelaGonzalezMarino
ca0cfbcb4e
keep march in bootrom generation without extensions ( #2121 )
2024-05-16 16:27:22 +02:00
Juan Granja
2182aee119
Update ariane_xilinx.sv ( #1954 )
2024-04-17 11:18:20 +02:00
Saute0212
5920e3d125
Add support for Nexys Video board ( #1925 )
2024-04-04 11:13:32 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Côme
83d94bbb69
transform rvfi types into macros ( #1921 )
2024-03-12 17:34:27 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
Yannick Casamatta
bc41a0b7fb
Modify rvfi probes for param change ( #1900 )
2024-03-07 18:34:27 +01:00
Côme
13dfa744d2
Parametrization step 1 ( #1896 )
2024-03-06 17:02:55 +01:00
Yannick Casamatta
1dec79464e
add csr in rvfi ( #1833 )
2024-02-24 00:10:23 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
Michael Platzer
78111aa5eb
config_pkg/csr_regfile: Add PMP entry rst vals & RO option ( #1769 )
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This commit adds three new fields to the `cva6_cfg_t` configuration
struct, which allows to specify reset values for the PMP configuration
and address CSRs as well as optionally making individual PMP entries
read-only. The purpose is to allow hard-wiring of certain regions'
privileges, which is explicitly allowed by the RISC-V Privileged
Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7).
2024-01-17 17:41:38 +01:00
André Sintzoff
3afe870d78
csr_regfile.sv: add RVB field for MISA ( fix #1734 ) ( #1760 )
2024-01-15 14:34:25 +01:00
AEzzejjari
36c105a50d
Code_coverage: condition RTL with the AxiBurstWriteEn parameter ( #1667 )
2023-12-01 22:59:12 +01:00
AEzzejjari
42f29c66bd
Code coverage: Add NonIdemPotence parameter ( #1647 )
2023-11-23 23:00:21 +01:00
AEzzejjari
1faaec09bc
Code_coverage: condition RTL with the debug parameter ( #1582 )
2023-10-31 17:35:59 +01:00
AEzzejjari
d92f0f76d0
Code_coverage: condition RTL with the U-MODE parameter ( #1583 )
2023-10-31 13:45:58 +01:00
AEzzejjari
4b67475fa4
Code_coverage: condition RTL with the S-MODE parameter ( #1574 )
2023-10-27 22:38:52 +02:00
Florian Zaruba
60dde07761
[license] Fix license headers in FPGA bootrom ( #1556 )
2023-10-20 09:19:41 +02:00
Luca Colagrande
74675b400c
Support multiple outstanding stores ( #1474 )
2023-10-19 22:03:54 +02:00
Cesar Fuguet
7de1345291
Add the HPDcache as cache subsystem ( #1513 )
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Add the HPDcache as another alternative for the cache subsystem.
The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.
2023-10-16 09:26:20 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter ( #1320 )
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* Variane as CVA6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix FPGA build
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix tipo in cva6.sv
* fix lint warnings
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix is_*_fpr functions
* remove blank lines
* set IsRVFI out of CVA6Cfg
* define config_pkg
* Fix ariane_pkg comments
* Fix Lint from André's feedbacks
* Fix parameter transmission
* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv
* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
2023-08-22 14:04:06 +02:00
JeanRochCoulon
716d21c424
Define AXI as cva6 input parameters ( #1315 )
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* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
2023-07-24 10:34:30 +02:00
JeanRochCoulon
1ddbab33e9
Use CVA6Cfg as cva6 parameter ( #1311 )
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* Use CVA6Cfg as cva6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Add information when defining CVA6Cfg type
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-07-20 13:36:11 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
Umer Imran
45259cfb6a
LINT: Initial changes for Lint warnings removal ( #1158 )
2023-04-24 08:22:56 +02:00
JeanRochCoulon
31948853c6
Replace WT_DCACHE define by CVA6ConfigCacheType localparam ( #1127 )
2023-03-21 14:18:18 +01:00
Kevin Eyssartier
c3848fa8a7
Bootrom.sv : upgraded to python 3 ( #1097 )
2023-03-07 18:30:10 +01:00
Nils Wistoff
7c92b68b92
Remove unused submodules ( #1023 )
2023-01-13 15:59:34 +01:00
Zbigniew Chamski
8a5898dce4
Vendorize CVA6 core submodules (common_cells, FPU with related sub-modules) ( #1007 )
2022-12-09 11:07:12 +01:00
Nils Wistoff
17743bc712
cache_subsystem: Parametrise AXI interface ( #982 )
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Parametrise the AXI interface of CVA6. With this PR, both cache subsystems support variable AXI address widths. The write-through cache furthermore supports variable AXI data widths. Moreover, this PR includes a modular AXI testbench for the WT cache to test the introduced changes. The following configurations of the WT cache have been verified:
XLEN Cacheline Width AXI data width AXI address width
64 128 64 64
64 128 128 52
64 512 128 64
32 512 256 48
32 64 32 48
2022-10-26 11:20:19 +02:00
Guillaume Chauvon
66f158dea0
FPGA: Add scripts to boot linux fpga ( #924 )
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Signed-off-by: Guillaume Chauvon<guillaume.chauvon@thalesgroup.com>
2022-06-28 09:59:51 +02:00
JeanRochCoulon
56f8c9f5fe
Add user field between memory and caches ( #857 )
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* wt_dcche_wbuffer.sv: fix assert
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Many files: Add user between memories and cva6
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Update std_nbdcache.sv
Make wb cache work
* Update setup.sh
Co-authored-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2022-04-20 12:47:07 +02:00
Luca Colagrande
75250868eb
wb_dcache: Forward atomic transactions to AXI ( #777 )
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* wb_dcache: Forward "atomic transactions" to AXI
* Correct bugs
* Forward LR/SC atomics
* Fix CI
* miss_handler: Route AMO port through arbiter
* axi_adapter: Correct LOAD AMOs handling
Accept read data only after (or together) handshake on B channel
* Restore old ID
* Correct atop encodings
* Correct AMOs AXI ID
* Correct wb_dcache testbench
Previously not comparing AMOs at all! Due to amo_exp_resp being 'x
* Realign and sign extend 32b request rdata
* Use axi_pkg definitions for ATOPs encoding
* Remove whitespace
* wb_dcache: Style corrections
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
2022-03-09 16:33:37 +01:00
Andreas Kuster
c72a9e5d56
Bump register interface to v0.3.1 ( #819 )
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* Bump register interface to v0.3.1
* Upgrade PLIC to upgraded register interface version v0.3.1
* Upgrade rv_plic submodule
* Add rv_plic upgrade to xilinx target. Fix indentations
* Try again (indentation)
* Add register_interface include
2022-02-10 14:19:12 +01:00
Nils Wistoff
741e82133d
ariane_testharness/ariane_xilinx: Fix AXI ID width ( #813 )
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- Fix the AXI ID width for the CLINT (previously `4`, now `5`)
- Parametrise the CLINT's AXI types
- Deprecate `axi_[master|slave]_connect` and move to AXI assign macros,
as they allow arbitrary AXI types
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-02-06 11:17:21 +01:00
Noah Huetter
da74358206
Remove debug module from devicetree ( #806 )
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* remove debug module from devicetree
* replace uart compatible string with one that uses the FiFos
* regenerate bootrom
* regenerate FPGA bootrom
Signed-off-by: Noah Huetter <huettern@iis.ee.ethz.ch>
Co-authored-by: Noah Huetter <huettern@iis.ee.ethz.ch>
2022-01-31 15:37:48 +01:00
Nils Wistoff
497236818f
ariane_xilinx: Fix xbar clock ( #799 )
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-01-22 08:47:26 +01:00
Michael Rogenmoser
4bdfa69d20
axi and common_cells upgrade (#791 )
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* Change questa version reference format
* bump common_cells to v1.23
* Bump axi to v0.31.0, replace axi_node with axi_xbar
* Bump register_interface for axi compatibility
* add prot signals to axi_lite for compatibility
2022-01-15 11:08:14 +01:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
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* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
