The instuction frontend has become an increasingly messy part an needed
cleaning-up. The current solution contains 2 x 32 bit instruction data
fifos and 1 x 64 bit address fifo. Hence, it should be significantly
more area efficient that the previous one. The interface to `id_stage`
is a ready/valid handshake. The credit based system has been replaced in
favour of a replay mechanism as it was very brittle and overly
pessimistic.
Branch-prediction has been cleaned up: The front-end was also partially
predicting on jumps, this could have potentially let to performance bugs
if the branch detection wasn't correct in the frontend.
In anticipation of cleaning up the branch-prediction a clear flag is no
longer needed. We know at prediction time whether the instruction is a
branch or not. This makes the effect of aliasing very unlikely.
The performance counters were accessible in user mode although
`mcounteren` or `scounteren` are not implemented. This commit moves the
writeable performance counters to machine mode. Access from
user/supervisor-space will trap as this is not implemented in Ariane.
When speculation is on it can happen that the core is trying to fetch
from a wrong, speculated address. Depending on the SoC this can cause
lock-ups. Solution until now was to flush all branchprediction which is
quite costly in terms of performance. This commit fixes this and lets
the `frontend` check whether the access is actually legal.
The "old" config system is quite rigid in terms of user
parameterization. To avoid adding more and more generics to the
parameter port I've packaged the parameters to use a single struct
`ariane_cfg_t` which can then be passed to all submodules in need of the
parameter value.
We can slowly transition to this new system. One drawback is the missing
capability to calculate parameters based on other parameters. Functions
would be needed to do so. Or, imho, the better approach would be a
Python script which generates the appropriate parameters.
The `debug_req_i` signal is associated to a new exception value which is
in the private reserved space of RISC-V. So it should never collide with
future exception values, although this should be transparent to software
anyway. Furthermore this patch makes the atomic commit logic simpler as
we are not getting any unexpected exceptions past the `id_stage`.
This patch is in preparation to fixing speculative reads to I/O regions.
This make execution more deterministic as we can decide early
whether the remaining pipeline is speculative or not. Furthermore it
removes a couple of logic gates during commit and clean-s up the tight
integration between `commit_stage` and `csr_regfile` which often lead
to combinational loops.
This patch is in preparation to fixing speculative reads to I/O regions.
* Add spike isa sim
* Fix AMO problem in verilator
* 🎨 Tidy up FPU wrapper
* Bump axi_exclusive submodule
* Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190)
* Refactor serpent AXI adapter
* Disable FPU in OpenPiton by default
* Bump dbg and atomics submodules
* Fix cache testbenches (interface change)
* FPGA bootrom changes for OpenPiton SDHC
* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD
* Testing barrier-based synchronisation instead of CLINT-based
* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707
* Add MAX_HARTS switch to makefile
* Fix gitlab CI
* Revert standard FPGA bootrom
* Update Flist
* Make UART_FREQ a parameter
* Fix typo in tb.list and an error in define switch in ariane_pkg
* Copy over SD-driver in bootloader from @leon575777642
* Fix compilation issues of bootrom
* Change signal name in serpent periph portlist
* Correct generate statement in serpent dcache memory
* Add Piton SD Controller, FPGA fixes
* Fix race condition in dcache misshandler
* Add tandem spike to Make flow
* Remove OpenPiton SD Card controller again
* Refactor serpent AXI adapter
* Disable FPU in OpenPiton by default
* Bump dbg and atomics submodules
* Fix cache testbenches (interface change)
* FPGA bootrom changes for OpenPiton SDHC
* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD
* Testing barrier-based synchronisation instead of CLINT-based
* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707
* Add MAX_HARTS switch to makefile
* Fix gitlab CI
* Revert standard FPGA bootrom
* Update Flist
* Make UART_FREQ a parameter
* Fix typo in tb.list and an error in define switch in ariane_pkg
* Copy over SD-driver in bootloader from @leon575777642
* Fix compilation issues of bootrom
* Change signal name in serpent periph portlist
* Correct generate statement in serpent dcache memory
* : Fix PITON_ARIANE define issues
* Fix write-back / cache read collision issue in serpent dcache.
* Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment).
* Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane.
* Fix assertion in icache.
* Correct JTAG timing constraints.
* Fix parameter type in fpga toplevel (fix#168).
* Remove conflicting bootrom from fpga file list.
* This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs).
* Fix byte offset of IPIs in CLINT
* Disable DCache flushes on fence for write-through cache (not needed in that case)
* Fix blocking assignments in ff process.
* Fix register access issue in debug mode, only affects A0 (fix#179).
* Fix multiple driver issue in PLIC
* Do not assume replicated data in serpent dcache when reading from an NC region.
* Another byte offset fix in IPIs (CLINT)
* Add AXI64 compliance switch to dcache_mem
* Fix genesys 2 constraints
* Map serpent atomic requests onto AXI atomic/exclusive transactions.
* Cleanup of AXI memory plumbing, add separate AXI adapter module.
* Remove unneeded interface signals, increase wbuffer #pending tx
* Fix verilator compilation issues in AXI adapter.
* Delete unnecessary constraint
* Delete duplicate module instance
* Update gitlab CI script
* Small fixes to make riscv atomics work with serpent_axi_adapter.
* Update travis and gitlab-ci scripts
* Register b responses for better timing.
* Remove fpu div submodule, update Makefile paths and src lists
* Constant bits in haltsum reduction must be 1 (AND reduction).
* Switch to DTM from riscv-dbg submodule
* Further cleanup fixes in AXI/serpent atomics
* Bump riscv-dbg version
* Add atomic adapter as submodule
* Change UART frequency
* Add atomic memory adapter
* Bump AXI exclusive submodule version
* Re-name ariane_next to ariane-dev
* Switch to official `atop` branch on `axi_node`
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
- Don't increment instret on exception
- Align cycle counter with instret counter (-> IPC 1 as in Spike)
- Add mock uart functionality
- Make the preloading elf a plus-arg
