51 commits

Author	SHA1	Message	Date
Mathieu Gouttenoire	3d00079c19	Prepare for LLVM (#2251)	2024-06-14 11:12:03 +02:00
JeanRochCoulon	cb6211bbb8	Remove cv32a6_embedded configuration (#2246)	2024-06-14 08:30:17 +02:00
JeanRochCoulon	4391fc4b14	Use cv32a6_imac_sv32 to generate FPGA bitstream (#2229)	2024-06-11 16:25:07 +02:00
Mathieu Gouttenoire	ade4c85e13	Remove extra -v in smoke-tests.sh (#2207)	2024-06-06 16:51:17 +02:00
xiaoweish	8cb7a8a4ed	fix gcc-14 compile error on: implicit-function-declaration, implicit-int (#2159)	2024-05-28 07:04:10 +02:00
slgth	9f4b2f7179	New target with MMU: cv64a6_mmu (#2149)	2024-05-24 13:39:00 +02:00
Cesar Fuguet	f32f51777f	Add in Github's CI a 64-bit configuration of the CVA6 using the HPDcache and restore WB cache test (#2114)	2024-05-21 09:51:10 +02:00
Jalali	95ad5fb83e	[HOT FIX] : Fix csr tests timeout (#2132)	2024-05-20 20:11:10 +02:00
Cesar Fuguet	0c2108845a	Allow to pass custom location for the Boost library for Spike (#2082)	2024-04-29 12:04:20 +02:00
Guillaume Chauvon	5e4bb5f2de	Fix DV_OPTS by adding UVM_VERBOSITY flag (#2080)	2024-04-26 14:33:33 +02:00
MarioOpenHWGroup	71ef48804a	[RVFI] Optimize CSRs (#1999)	2024-04-15 16:29:07 +02:00
Côme	f886713754	User config generator becomes a Python tool to work with configs (#2003)	2024-04-04 15:56:29 +02:00
Guillaume Chauvon	f884347db4	Add debug_disable=1 to match default configuration of cva6.py (#1977)	2024-03-29 14:44:03 +01:00
MarioOpenHWGroup	62bdf11594	Bump core-v-verif d94f0de and fix questa simulator (#1915)	2024-03-21 19:02:41 +01:00
André Sintzoff	9a713c3b17	smoke-tests.sh: run first I-ADD-01 test for cv64a6_imafdc_sv39 (#1934)	2024-03-15 18:14:32 +01:00
valentinThomazic	a4fc0e9f99	Check tools version before simulation (#1899)	2024-03-07 16:34:10 +01:00
Zbigniew Chamski	16bdcda07c	Improve environment setup. Fix Verilator installation process. (#1864) ... * verif/sim/setup-env.sh: Double-quote variable values. Install Verilator in 'tools/verilator' by default. Add SPIKE_PATH to PATH. * verif/regress/install-verilator.sh: By default use per-version dirs to build and install Verilator. Add and improve configuration messages.	2024-03-05 17:18:33 +01:00
Jalali	ce0ab81630	Connect CSRs info from RVFI_CSR in the testbench & update simulation target (#1879)	2024-02-28 16:20:24 +01:00
Jalali	5dd04829e3	ISA functional coverage : Add directed tests (#1855)	2024-02-21 09:31:54 +01:00
valentinThomazic	cedc21bb35	fixed Verilator detection by tests (#1854)	2024-02-20 19:30:40 +01:00
Jalali	33a7a8207a	GEN_TESTS: Add --priv option to command generated tests (#1831)	2024-02-14 10:39:01 +01:00
JeanRochCoulon	de5d0d7ed4	cv32a65x (#1799)	2024-02-01 13:11:45 +01:00
JeanRochCoulon	56f6216430	Run simulation for embedded configuration (#1798)	2024-01-30 11:06:54 +01:00
Siris Li	ef5e378c93	Fix bug in install-spike.sh (#1763)	2024-01-18 23:32:32 +01:00
MarioOpenHWGroup	8b6e8295f8	Add priv level to cva6.py and fix smoke-tests (#1768)	2024-01-17 23:14:19 +01:00
valentinThomazic	706daa0a3b	removed the usage of install-cva6.sh and add setup-env.sh (#1741)	2024-01-03 13:42:23 +01:00
MarioOpenHWGroup	809bcf4ed0	Update verilator to v5.018 (#1699)	2023-12-12 14:02:59 +01:00
valentinThomazic	61fb0cdd5c	set default NUM_JOBS value to be the same accross all scripts (#1688)	2023-12-08 16:57:46 +01:00
valentinThomazic	34f631ffc5	remove hard-coded gcc options (#1652)	2023-11-23 23:35:20 +01:00
Jalali	b143be15d2	Add more load_store generated tests to improve CC (#1641)	2023-11-17 18:14:38 +01:00
Jalali	f9c7542e84	Generate Zcb extension instructions (#1617)	2023-11-14 08:18:28 +00:00
Jalali	5e68fc0a3f	Add more unmapped instructions tests with more combinations (#1622)	2023-11-13 11:44:00 +01:00
MarioOpenHWGroup	220f534b6d	Spike Tandem Implementation using VCS simulator (#1561)	2023-11-09 19:29:24 +01:00
Jalali	5a7bbafdab	Add unmapped Instructions tests to improve code coverage (#1608)	2023-11-08 16:08:19 +01:00
Jalali	c31ebcd321	Add CSRs tests for embedded config (#1601)	2023-11-07 14:09:08 +01:00
Côme	168292364a	use embedded config to run coremark (#1602)	2023-11-07 14:06:10 +01:00
Côme	b2a59c9617	Convert DV into a submodule (#1591)	2023-11-03 11:20:08 +01:00
Jalali	797f0a90c6	Enable ZBA, ZBB, ZBC, ZBS in cva6 env & generated tests (#1587)	2023-10-31 19:55:08 +01:00
JeanRochCoulon	18e9d8ea8e	Reduce the number of executed tests (#1580) ... As the execution of this job is longer than other jobs, reduce the number of executed jobs.	2023-10-31 09:36:28 +01:00
Jalali	e2a5250473	Updates to match the latest version of RISCV-DV (#1576)	2023-10-30 14:10:58 +01:00
Fatima Saleem	38b1da26c3	adding bitmanip and atomic arch-tests (#1560)	2023-10-20 16:03:12 +02:00
MarioOpenHWGroup	3e72504d97	Get spike from cvv repo (#1544) ... * Change target on install-spike * Delete vendor/riscv/riscv-isa-sim	2023-10-18 17:39:40 +02:00
Jalali	03490e43a8	Update tests' description & enable hvp for coverage report (#1532)	2023-10-17 22:00:47 +02:00
Jalali	5eac75842d	Change STEP1 target with the embedded target (#1519)	2023-10-09 22:12:24 +02:00
Côme	fb7b3c8b26	fix dv for recent python versions (#1501) ... With newest Python version, cva6.py cannot find dv.scripts module. This modifications adds an empty `__init__.py` in dv so that it can be found by Python 3.9.	2023-10-05 22:08:00 +02:00
Zbigniew Chamski	1683c818c4	Streamline installation process (Spike and toolchain variables, README file). (#1468)	2023-09-26 16:51:03 +02:00
Ammar Khan	72143ef0a9	SV32-DV-Plan Execution (#1376)	2023-09-21 21:03:07 +02:00
Côme	76c965320b	Heavy CI refactoring (#1455)	2023-09-19 19:40:41 +02:00
Côme	3e5ebdf4f4	Fix cleaning in coremark and dhrystone (#1396)	2023-09-13 22:35:19 +02:00
Jean-Roch Coulon	b13530ccbc	fix regress tests and makefiles ... Co-authored-by: Côme Allart <come.allart@thalesgroup.com>	2023-09-07 11:38:34 +02:00