53 commits

Author	SHA1	Message	Date
Munail Waqar	f7dd49efa5	Adding support for Scalar Crypto Extension (Bitmanip instructions for Cryptography, Zbkb) (#2653) ... Introduction This PR adds support for Zbkb extension in the CVA6 core. It also adds the documentation for this extension. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will be followed by other PRs that will add complete support for the Zkn - NIST Algorithm Suite extension. Implementation Zbkb Extension: Added support for the Zbkb instruction set. It essentially expands the Zbb extension with additional instructions useful in cryptography. These instructions are pack, packh, packw, brev8, unzip and zip. Modifications 1. A new bit ZKN was added. The complete Zkn extension will be added under this bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set. 2. Updated the ALU and decoder to recognize and handle Zbkb instructions. Documentation and Reference The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for the Zbkb instruction was also added. Verification Assembly Tests: The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior. The tests include: pack-01.S packh-01.S packw-01.S brev8-01.S unzip-01.S zip-01.S	2024-12-18 22:35:41 +01:00
Jalali	5b1c194cb7	UVM_ENV : Clean up CVA6 UVM env (#2633) ... This MR do some cleaning on the uvm env : * fixing typo * remove unused code * printing in the right place	2024-11-26 15:30:48 +01:00
Jean-Roch Coulon	9cfadbeded	Create dedicated linker scripts for cv32a65x configuration. When another configuration is targeted, the default linker script is used (config/genxxx/linker/link.ld). When hwconfig is targeted, linker scripts are recopied into hwconfig directory. ... Keep only one unique linker script: link.ldi. Remove test.ld file.	2024-10-23 18:24:38 +02:00
Jean-Roch Coulon	1d0076eec3	smoke-hwconfig: run with vcs-uvm and use return0 test to speed-up CI light stage timing execution	2024-10-23 18:24:38 +02:00
JeanRochCoulon	45eaace82b	Revert "Multicommits to shorten smoke-tests duration, to declare VLEN as para…" (#2564) ... This reverts commit 0877e8e446.	2024-10-23 18:12:49 +02:00
JeanRochCoulon	0877e8e446	Multicommits to shorten smoke-tests duration, to declare VLEN as parameter, to improve coremark results, to implement spike.yaml/linker dedicated to 65x (#2563) ... - FIX: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN - Declare VLEN as new CVA6 parameter - smoke-hwconfig: run with vcs-uvm and use return0 tests to speed-up CI light stage timing execution - Use dedicated linker scripts for 65x configuration. - Use dedicated spike.yaml for 65x configuration. - Set BHTEntries=128, cache=WT, scoreboard entries=8 to improve Coremark and Dhrystone results - Run 4 iterations of coremark to improve results	2024-10-23 17:56:06 +02:00
Jalali	7394941220	Interrupt verif : Implement clear mechanism in interrupt's agent (#2527) ... * INTERRUPT VERIF : Implement interrupt clear mechanism * Interrupt Verif : Add irq_timeout to exit when we failed to write into irq_add Also change uvm_warining to uvm_info * Fix comment	2024-10-16 11:50:56 -04:00
Anouar	9c3aea232f	Performance tb (#2543)	2024-10-11 16:57:45 +02:00
Jean-Roch Coulon	b744f9bb09	Create job dedicated to benchmark CVA6	2024-10-08 21:14:33 +02:00
Zbigniew Chamski	f974e105bf	Add a basic mechanism for interrupt acknowledge. (#2502)	2024-09-19 18:31:42 +02:00
Zbigniew Chamski	89eb77a249	[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem. Add workaround for AXI end-of-test asserts. (#2436)	2024-08-19 11:09:32 +02:00
xiaoweish	0c60bc6e3d	Add debug_test to cva6 (#2339)	2024-08-02 08:50:50 +02:00
Guillaume Chauvon	81671e39fa	Fixes and Update CVXIF non regression tests, regression and TB (#2424)	2024-08-01 16:06:24 +02:00
valentinThomazic	77c6cc328d	fix CI regression testlists (#2378)	2024-07-22 17:29:25 +02:00
Jalali	6c0e3f82c5	Verif: Add load hazard instructions (#2354)	2024-07-15 12:39:52 +00:00
Guillaume Chauvon	8fa590b5c3	CVXIF 1.0.0 (#2340)	2024-07-12 10:53:18 +02:00
Jalali	dc9dc150e7	Increase supported PMP entries in UVM testbench (#2344)	2024-07-10 11:54:29 +02:00
Jalali	2616d5e649	add UVM interrupt agent (#2309)	2024-07-05 11:54:34 +02:00
Jalali	9ebe42f033	Add illegal instruction to cover corner case in decoder (#2307)	2024-07-02 17:40:45 +02:00
Jalali	212c14e4b4	CSR verification : modify coverage based on new specification (#2261)	2024-06-14 14:01:23 +02:00
Mathieu Gouttenoire	3d00079c19	Prepare for LLVM (#2251)	2024-06-14 11:12:03 +02:00
JeanRochCoulon	cb6211bbb8	Remove cv32a6_embedded configuration (#2246)	2024-06-14 08:30:17 +02:00
AEzzejjari	1c828c0a16	Connect the new AXI agent with CVA6 (#2182)	2024-06-03 14:42:37 +02:00
xiaoweish	4e9c6ac9a3	Update testlist yaml with #2073 PR using yaml anchor/alias (#2146)	2024-05-23 11:25:04 +02:00
JeanRochCoulon	dd763b4f4c	Rename FpuEn into RVF (#2109)	2024-05-15 09:16:44 +02:00
Jalali	130a526f3b	ISA : Cover zext with instr[24:20] != 0 (#2085)	2024-04-30 17:02:37 +02:00
xiaoweish	3919e79f8f	Implement YAML anchor/alias for streamlined testlist structure (#2073)	2024-04-28 23:00:22 +02:00
Jalali	5971fc755a	ISA coverage status (#2066)	2024-04-22 17:51:28 +02:00
André Sintzoff	1e93175dd4	testlists for cv32a65x: add files (#2037)	2024-04-12 17:47:03 +02:00
Côme	f886713754	User config generator becomes a Python tool to work with configs (#2003)	2024-04-04 15:56:29 +02:00
valentinThomazic	3dc1f23a9d	Support Spike Parameters in cva6.py and bump core-v-verif (#1976)	2024-04-02 10:26:25 +02:00
MarioOpenHWGroup	08d098bf51	[RVFI] Change CSR implementation (#1952)	2024-03-25 12:15:18 +01:00
MarioOpenHWGroup	62bdf11594	Bump core-v-verif d94f0de and fix questa simulator (#1915)	2024-03-21 19:02:41 +01:00
Jalali	6851499b18	Add directed Tests for jump instructions (#1933)	2024-03-15 15:16:21 +00:00
Rohan Arshid	c827c3b770	Zcmp extension support (#1779)	2024-03-13 11:37:49 +01:00
Jalali	9c4a3c37d6	Remove mcountinhibit from csr_test and UVM env (#1863)	2024-02-21 19:13:57 +01:00
Jalali	5dd04829e3	ISA functional coverage : Add directed tests (#1855)	2024-02-21 09:31:54 +01:00
AEzzejjari	5e80c104c9	AXI agent: Connect the the new AXI agent (#1817)	2024-02-18 23:31:44 +01:00
Jalali	3d7e417bce	Functional coverage : Add cross to illegal and exception coverage models (#1839)	2024-02-18 23:30:11 +01:00
MarioOpenHWGroup	c7f0eaf0d8	Bump verif/core-v-verif from fd68dfd to c7d2077 (#1828)	2024-02-13 14:20:21 +01:00
Jalali	c2d9d4b283	MTVAL : Remove MTVAL CSR from CVA6 UVM environment (#1788)	2024-01-26 16:47:15 +01:00
Jalali	179084315f	ISACOV : Update seq Directed test, and remove failing tests from regression (#1787)	2024-01-26 15:02:31 +01:00
Jalali	4cd5c4a7e8	Add overflow counter test & fix reset value (#1746)	2024-01-05 13:29:48 +01:00
Jalali	447d01a163	[Verif] Clear MIP CSR to avoid trapping in CSR tests (resume #1660) (#1661)	2023-11-29 15:09:10 +01:00
Jalali	6254dfa721	Clear MIP CSR to avoid trapping (#1660)	2023-11-29 13:55:50 +01:00
MarioOpenHWGroup	220f534b6d	Spike Tandem Implementation using VCS simulator (#1561)	2023-11-09 19:29:24 +01:00
Jalali	c31ebcd321	Add CSRs tests for embedded config (#1601)	2023-11-07 14:09:08 +01:00
Fatima Saleem	38b1da26c3	adding bitmanip and atomic arch-tests (#1560)	2023-10-20 16:03:12 +02:00
Côme	e8022778b7	ci: reorganize jobs (#1517)	2023-10-09 22:35:23 +02:00
sai krishna pidugu	c6877587ea	CV32A6 CSR Access Verification (#1380)	2023-09-28 14:11:55 +02:00