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dependabot/pip/doc/jinja2-3.1.3

dvsim_report

gh-readonly-queue/master/pr-2051-90ee203a9a44773061e824711d281d2c3557a200

gsoc/2020/pointer-authentication

harryc_ci_test

marnovandermaas-patch-1

master

pmp-coverage-improvement

pmp_ci_run_and_cov_merge_fixes

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pulpinov1

pulpissimo

revert-2226-fix_counter_reset_value

riscv-formal

rtl_log_fix

test_csr_cov_improvements

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pulpino-v1.0.0

pulpissimo-v1.0

pulpissimo-v1.0.0

pulpissimo-v1.0.1

pulpissimo-v4.1.0

pulpissimo-v6.0.0

pulpissimo-v6.1.0

pulpissimo-v6.1.1

1211237494 Remove vectorial stuff from multiplier Sven Stucki 2015-09-30 18:40:56 +02:00
88fb2adac3 Add many ALU instructions from OR10N Sven Stucki 2015-09-30 18:23:42 +02:00
715265d61d Add MAC with subword selection Sven Stucki 2015-09-30 16:50:03 +02:00
076930ad64 Correctly deassert mac_en_o too Sven Stucki 2015-09-30 16:31:26 +02:00
66e2c9b48b Edit comments in decoder Sven Stucki 2015-09-30 16:23:38 +02:00
e001a6e745 Not taken branches do no longer waste cycles Andreas Traber 2015-09-30 13:06:22 +02:00
fbd897a233 Fix forwarding of rs3 Sven Stucki 2015-09-29 17:45:21 +02:00
8fa5f6a522 Add reg-reg and post-increment load/stores to tracer Sven Stucki 2015-09-29 14:10:29 +02:00
9ff25b5a1d Add MAC instruction, update regc (i.e. rs3) position Sven Stucki 2015-09-25 14:14:01 +02:00
3a992372d6 Merge branch 'rvc18' Sven Stucki 2015-09-25 13:19:41 +02:00
1aa8b78a73 Prefetcher now tells the core when it is safe to shut down Andreas Traber 2015-09-24 16:32:17 +02:00
4571bc30ae Make instr_addr_o in prefetcher independent of instr_rvalid_i Andreas Traber 2015-09-24 13:20:11 +02:00
efb607a792 Fix exception problem after stages are more independent Andreas Traber 2015-09-24 13:16:18 +02:00
415546609e Simplify rdata output from prefetcher, we can simply use the higher part of rdata_o for rdata_unaligned_o, it's the same after all, always Andreas Traber 2015-09-24 09:59:04 +02:00
2f89182e8b Clear prefetch bit when branch is incoming Andreas Traber 2015-09-24 09:32:28 +02:00
cc90e85471 Fix RVC handling in prefetch_L0_buffer Andreas Traber 2015-09-23 17:24:27 +02:00
b41b2a697d Further cleanups, try to make the code a bit easier to understand... Andreas Traber 2015-09-23 15:57:57 +02:00
d988f06f0e Fixed synopsis syntax error Flo Zaruba 2015-09-23 15:44:03 +02:00
88614ea124 Fix id_valid signal propagation to exception controller Andreas Traber 2015-09-23 15:33:02 +02:00
a3256c4df2 Fix small error in prefetcher where GNT occur one cycle after we wanted to prefetch Andreas Traber 2015-09-23 15:32:30 +02:00
b5c885b027 Cleanup compressed decoder Sven Stucki 2015-09-23 14:12:34 +02:00
6ececfc676 Update compressed_decoder to RVC v1.8 Sven Stucki 2015-09-23 14:11:42 +02:00
9ceeb15bc8 This fixes the instruction fetch miss performance counter Andreas Traber 2015-09-22 16:35:16 +02:00
072cd65e65 Change indentation of prefetch buffer to match RI5CYs style Andreas Traber 2015-09-22 12:38:34 +02:00
74f5d5c0a4 Integrated prefetch_L0_buffer from Igor Andreas Traber 2015-09-22 11:14:16 +02:00
49f7249b0a Decentralize stall control Andreas Traber 2015-09-21 18:26:08 +02:00
e98e47b9e5 Something went wrong in the cherry-pick, remove remains of timer Andreas Traber 2015-09-18 13:12:56 +02:00
90cc39a9ca Exception controller update Flo Zaruba 2015-09-17 13:47:34 +02:00
d274068643 Cherry pick 1 Flo Zaruba 2015-09-17 13:51:54 +02:00
8fe67b303d Run through linter and do some cleanup Andreas Traber 2015-09-15 13:08:26 +02:00
9858caff47 Separated decoder and controller and cleanup Andreas Traber 2015-09-15 12:52:15 +02:00
d27a2a3f63 Various debug related improvements Andreas Traber 2015-09-15 09:46:04 +02:00
10ae9df25a Remove movhi ALU opcode, it is of no use for RI5CY Andreas Traber 2015-09-14 15:53:17 +02:00
d2a549bfae Fix misaligned access, they did not correctly forward and used the wrong increment... Andreas Traber 2015-09-14 12:46:46 +02:00
1b2a80e7c9 Oops... is_compressed can of course no longer be generated in id stage but must be pipelined from if stage Andreas Traber 2015-09-11 17:42:15 +02:00
52d3608a93 Simplify exception controller and make sure external IRQs work as well Andreas Traber 2015-09-11 14:06:38 +02:00
0608b98440 Make illegal instruction exceptions work again Andreas Traber 2015-09-11 13:14:56 +02:00
e41c7b96be Change LSU to use correct protocol Andreas Traber 2015-09-10 13:05:24 +02:00
6fb05eab34 Rename instr_core_intf to prefetch_buffer, add if_busy signal again Andreas Traber 2015-09-10 09:54:43 +02:00
84ea2c90ee Fix aborting on instr core interface Andreas Traber 2015-09-09 15:53:00 +02:00
463e74cf05 Only stall IF fsms when absolutely necessary Andreas Traber 2015-09-09 14:28:07 +02:00
847b652ce5 Change IF fifo depth to 3 to get performance from old IF back Andreas Traber 2015-09-09 13:50:03 +02:00
db82a7ab8e Fix problem with unaligned compressed access Andreas Traber 2015-09-09 13:44:53 +02:00
e0ea57968b Prefetcher basically done, works in pulpino without rvc Andreas Traber 2015-09-09 12:46:53 +02:00
79bce5b31b Add a basic datasheet for RI5CY Andreas Traber 2015-09-09 18:35:07 +02:00
b347299f31 Move compressed decoder/expander to IF stage Andreas Traber 2015-09-08 19:33:10 +02:00
f5e1020f57 Add performance counter for compressed instructions Sven Stucki 2015-09-08 17:24:39 +02:00
a330a8fe70 Improve inline comments in if_stage Andreas Traber 2015-09-07 09:09:22 +02:00
216362365c Fix hwloop we Sven Stucki 2015-09-07 11:53:21 +02:00
c2b519786b Merge branch 'hwloops' Sven Stucki 2015-09-07 03:41:28 +02:00
b5aea15659 Finish hwloops addition Sven Stucki 2015-09-07 03:40:28 +02:00
82afb4c839 Remove another unnecessary signal Sven Stucki 2015-09-05 18:15:18 +02:00
24f0a588f5 More cleanup, remove unused signal Sven Stucki 2015-09-05 16:33:51 +02:00
f9d0911329 Cleanup ID Sven Stucki 2015-09-05 16:00:41 +02:00
a6dc8271e9 Wire up hwloops correctly, other small fixes Sven Stucki 2015-09-05 03:37:50 +02:00
4f06b67e65 Simplify instr core interface Andreas Traber 2015-09-04 15:52:35 +02:00
adb40aef43 Make instr_req_o signal dependent only on state Andreas Traber 2015-09-04 13:54:19 +02:00
87e2eec128 Move hwloop regs into ID stage, WIP Sven Stucki 2015-09-03 13:39:11 +02:00
77ef44a82f Separate jump target calculation from jump_in_id Sven Stucki 2015-09-03 02:08:48 +02:00
2c2ad21c85 Reroute hwloops signals, fix counter mux Sven Stucki 2015-09-02 18:32:03 +02:00
82eaaf86be Cleanup unneeded signals and dead code Sven Stucki 2015-09-02 18:07:44 +02:00
e305a8e648 Harmonize indentation in controller Sven Stucki 2015-09-02 17:11:23 +02:00
b81c7c6c57 Fix indentation in riscv_core.sv, better defaults Sven Stucki 2015-09-02 16:31:16 +02:00
03a43245c7 Oops, fetch_addr_Q was multiply driven Andreas Traber 2015-09-02 10:27:52 +02:00
3a7d4044e9 Fix width of irq_enable signal Andreas Traber 2015-09-02 09:30:03 +02:00
ccb4497b36 Use 'x to simplify synthesis Andreas Traber 2015-09-02 09:25:06 +02:00
5aa77089fa Move LSU related signals out of ex_stage and alu and put them inside LSU Andreas Traber 2015-09-02 08:55:44 +02:00
a617bc496e Fix compile errors from last commit, fix synthesis warnigns and remove unused signals Andreas Traber 2015-09-02 08:38:25 +02:00
3a4ddb2af3 New CSR implementation, fix irq_enable signal Sven Stucki 2015-09-02 01:37:19 +02:00
bb693c8e6b Add support to debug unit to set the Program Counter Andreas Traber 2015-09-01 18:18:02 +02:00
68a9171fb3 Add missing branch instruction to compressed decoder Andreas Traber 2015-09-01 17:24:12 +02:00
7e81d60510 Add two missing compressed instructions Andreas Traber 2015-09-01 14:51:19 +02:00
bc51ae9305 Add sensible default in compressed decoder for one case Sven Stucki 2015-09-01 12:58:24 +02:00
116b5f4641 Debug support: Make single-stepping work again Andreas Traber 2015-08-31 17:00:26 +02:00
d5802e5e62 Simplified fetch logic a little bit Andreas Traber 2015-09-01 09:53:03 +02:00
fbf8874e13 Simplify jump_target mux Andreas Traber 2015-09-01 08:47:31 +02:00
2c72b487dc Readd ALU flag to EX stage, use it for branch decision Sven Stucki 2015-08-31 13:06:43 +02:00
4015362ee8 Remove TCDM_ADDR_PRECAL and some other cleanup Sven Stucki 2015-08-31 11:28:34 +02:00
6aa40c336d Add hwloop decoding Sven Stucki 2015-08-31 03:13:14 +02:00
5a38967a0c Cleanup space madness Sven Stucki 2015-08-31 02:57:38 +02:00
5a821e643b Cosmetic changes in hwloop controller, ID and includes Sven Stucki 2015-08-31 01:33:54 +02:00
6cdfde93c7 Fix hwloop code indentation Sven Stucki 2015-08-31 00:00:21 +02:00
3c89d1400d Initial commit of OR10N hwloop controller and regs Sven Stucki 2015-08-30 23:57:53 +02:00
387642f094 Fix WFI instruction Andreas Traber 2015-08-31 10:55:16 +02:00
b84dde00b8 Fix potential problem with core_busy_o, it is now also set when an instruction request is in flight and not only when we are decoding Andreas Traber 2015-08-31 10:24:39 +02:00
88b91c20c5 Rework pipeline flushes and exceptions Andreas Traber 2015-08-31 10:02:55 +02:00
dd57252f60 Improve display for illegal instructions Andreas Traber 2015-08-31 09:16:03 +02:00
5f3b73ab8a Remove all case inside from decoder Sven Stucki 2015-08-28 18:50:22 +02:00
2c93147fc3 Remove dead wb_stage file and module Andreas Traber 2015-08-28 17:17:46 +02:00
1cbbcfb90b Fix linting errors/warnings and remove dead signals Part #2 Andreas Traber 2015-08-28 17:15:55 +02:00
d0f4ac75fb Fix linting warnings and errors Remove lots of dead code Part #1 Andreas Traber 2015-08-28 16:48:20 +02:00
de0d3dc76d Small cosmetics on IF stage Sven Stucki 2015-08-28 15:41:44 +02:00
18e0373468 Take #3, don't mix blocking and non-blocking assignments Andreas Traber 2015-08-28 14:01:39 +02:00
5ea5e01990 Synthesis problems... take #2 Andreas Traber 2015-08-28 13:55:50 +02:00
6cf4b2f229 Fix PCMR for synthesis... Andreas Traber 2015-08-28 13:52:59 +02:00
f54b164778 Fix external performance counters Andreas Traber 2015-08-28 13:43:23 +02:00
0188441cc7 Silence exception warning Andreas Traber 2015-08-28 11:31:09 +02:00
d99621f699 Add performance counters Andreas Traber 2015-08-28 09:57:37 +02:00
8c4a99b5ec Fix jalr stall and make jump more efficient Andreas Traber 2015-08-27 13:57:13 +02:00
4baf8eaad9 Added missing compressed instruction: c.slt Andreas Traber 2015-08-27 09:39:22 +02:00