mohammadshahidzade
4efa1e2d03
Os fixes6 ( #29 )
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* Support for atomic extension A
* Support instruction fence extension Zifencei
* Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions
* Support address translation
* Fixes interrupts and exception handling
* Adds interrupt controllers
* Support coherent multicore systems through a new data cache and arbiter
* Multiple bugfixes
* Adds new scripts for example systems in Vivado and LiteX
* Removes legacy, unused, and broken scripts, examples, and files
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Co-authored-by: Chris Keilbart <keilbartchris@gmail.com>
Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca>
Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com>
Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
2025-03-11 16:06:16 -07:00
Chris Keilbart
98f8be7d1e
Add FPU
2024-03-19 09:58:22 -07:00
Chris Keilbart
f3b1a453fb
Merge WSTRB fix
2024-03-19 09:53:31 -07:00
Eric Matthews
8769842249
Add dcache cbo instruction support
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-05-02 14:58:26 -04:00
Eric Matthews
1d0ac14e70
Cleanup unit writeback group and ID assignment
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-28 19:51:18 -04:00
Eric Matthews
89810cec57
Decode/Issue cleanup
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-28 14:18:35 -04:00
Eric Matthews
e003b51f95
Convert id_metadata from inferred LUTRAMs to LUTRAM modules
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-04-11 19:35:04 -04:00
Eric Matthews
5876454ab7
switch sim stats to use ISA rd for stall sources
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-02-27 12:57:52 -05:00
Eric Matthews
b8ee58c515
cleanup naming of retire signals
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-02-25 14:58:07 -05:00
Eric Matthews
f15fe83a9c
Store queue data forwarding restructure
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-02-01 23:08:13 -05:00
Eric Matthews
6cf0d84c3e
Move decode logic to respective units
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-01-30 19:42:30 -05:00
Eric Matthews
1e9343a91c
Restructure registerfile muxes
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2023-01-20 19:30:04 -05:00
Eric Matthews
4d42d3445d
Simulation tracing improvements
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-11-14 12:03:35 -05:00
Florian Meisel
f6a593402a
Update uses of l2_requester_interface::be
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-> examples/litex/l1_to_wishbone.sv
-> test_benches/verilator/AXI_DDR_simulation/axi_l2_text.sv, .cc
Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
2022-09-09 16:57:55 +02:00
Eric Matthews
95bc8d244c
Reduce data cache latency
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-07-05 15:38:36 -04:00
Eric Matthews
6aeac17b9d
Rework simulation stats
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-05-27 16:28:17 -04:00
Eric Matthews
1ffbacbb51
verilator optional PC trace support
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-05-12 22:22:45 -04:00
Eric Matthews
b87cb6ca16
load-store code cleanup
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-05-12 10:46:10 -04:00
Eric Matthews
087766b3bc
Wishbone bus signals renamed
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-04-29 13:59:10 -04:00
Eric Matthews
08e59f20eb
Added support for optional instruction buses
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-03-31 16:38:30 -04:00
Eric Matthews
9cff8c5afb
renamed occurrences of taiga to cva5
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-03-05 12:53:49 -08:00
Eric Matthews
97368c431d
added generate labels
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Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-02-10 11:17:01 -08:00
Eric Matthews
e2f162526a
fence logic load-store-unit
2022-01-18 11:29:35 -08:00
Eric Matthews
3e63a4c657
interrupt rewire
2022-01-18 11:29:35 -08:00
Eric Matthews
dec39b9041
removed old lut_ram
2022-01-18 11:29:35 -08:00
Eric Matthews
9c3f22ee65
switch spec_table to 1w_mr lutram
2022-01-18 11:29:35 -08:00
Eric Matthews
5cb82d96f1
re-parameterization
2022-01-18 11:29:35 -08:00
Eric Matthews
d87f03bf29
verilator cleanups
2022-01-18 11:29:35 -08:00
Eric Matthews
667939ca3e
code cleanup
2022-01-18 11:29:35 -08:00
Eric Matthews
678b6d2f08
package import refactor
2022-01-18 11:29:35 -08:00
Eric Matthews
c0ceb18d5f
simulation: visibility into architectural regfile
2022-01-18 11:29:35 -08:00
Eric Matthews
943b8bbc6e
added pause/resume behaviour to stat collection
2022-01-18 11:29:35 -08:00
Eric Matthews
78155870c1
seperated load and store queues
2022-01-18 11:29:35 -08:00
Eric Matthews
22bb15ed1f
early branch aliasing correction support
2022-01-18 11:29:35 -08:00
Zavier Aguila
71e69c87f7
Fixed how tracer values are being dumped.
2022-01-18 11:29:35 -08:00
Eric Matthews
a15921cdf3
makefile refactor
2020-07-29 10:29:14 -07:00
Eric Matthews
2bd7754acd
script parsing fixes
2020-06-07 14:13:23 -07:00
Zavier Aguila
fae4b40d89
DDR simulation
2020-06-03 20:39:35 +00:00
Eric Matthews
8ea982f1ab
lsq updates
2020-03-10 11:37:22 -07:00
Eric Matthews
bb534d617f
Added L2 arbiter to verilator test platform
2020-03-05 15:00:36 -08:00
Eric Matthews
1f61d77e43
Additional tracing support
2020-01-25 14:48:40 -08:00
Eric Matthews
0558c63557
div interface refactor
2019-11-19 18:06:20 -08:00
Eric Matthews
02377934ec
enabled assertions
2019-09-28 17:59:49 -07:00
Eric Matthews
5bd0f9eda1
additional tracing for branch predictor and increased flexibility for store forwarding
2019-09-24 13:39:32 -07:00
Eric Matthews
9903073465
Additional trace signals
2019-09-16 12:20:46 -07:00
Eric Matthews
63eb64ed8b
further verilator testbench changes
2019-09-11 17:30:42 -07:00
Eric Matthews
2713b8675a
Verilator test bench refactor
2019-09-10 15:42:53 -07:00
Eric Matthews
c0727257f4
Now always in-order commit
2019-09-01 15:39:59 -07:00
Eric Matthews
976ad3d5ee
embench benchmarks added and binary tool made more robust
2019-08-18 17:23:01 -07:00
Eric Matthews
c493c164b5
break conditions on issue of instruction not on appearance at decode stage
2019-07-23 14:44:46 -07:00
