43 commits

Author	SHA1	Message	Date
Anouar	ffddc147c1	OBI Agent and assertions integration (#2257)	2024-08-27 17:02:05 +02:00
MarioOpenHWGroup	4b51643826	TANDEM Configuration fixes (#2420)	2024-08-09 12:34:40 +02:00
xiaoweish	0c60bc6e3d	Add debug_test to cva6 (#2339)	2024-08-02 08:50:50 +02:00
Guillaume Chauvon	81671e39fa	Fixes and Update CVXIF non regression tests, regression and TB (#2424)	2024-08-01 16:06:24 +02:00
Guillaume Chauvon	8fa590b5c3	CVXIF 1.0.0 (#2340)	2024-07-12 10:53:18 +02:00
Jalali	2616d5e649	add UVM interrupt agent (#2309)	2024-07-05 11:54:34 +02:00
Jalali	702fedf23f	Fix issue #2479 #2468 (#2318)	2024-07-03 17:14:15 +02:00
Jalali	f18bac51b3	Bump CVV to fix issue 2484 (#2302)	2024-07-02 17:41:23 +02:00
xiaoweish	88f13c5874	Update uvml_mem use for core-v-verif's PR: 2480/2481/2482 (#2295)	2024-06-26 23:00:57 +02:00
MarioOpenHWGroup	c78ede91f9	Bump CVV 2465 and adapt cva6pkg (#2263)	2024-06-17 16:49:10 +02:00
CoralieAllioux	28e94e5ce3	[Xcelium flow] Clean DPI void function import (#2222)	2024-06-12 09:45:33 +02:00
Guillaume Chauvon	a5152b03a5	Add support for cv32a65x dedicated synthesis (#2178)	2024-06-04 10:58:09 +02:00
AEzzejjari	1c828c0a16	Connect the new AXI agent with CVA6 (#2182)	2024-06-03 14:42:37 +02:00
MarioOpenHWGroup	d89c5b6ba6	Disable misa we in rm (#2181)	2024-06-03 10:58:22 +02:00
MarioOpenHWGroup	d714d833cb	Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044)	2024-05-30 15:57:58 +02:00
Zbigniew Chamski	d1c6aab1f0	[UVM TB] Initialize information about DRAM address and size. (#2153)	2024-05-27 16:13:12 +02:00
Jalali	e7f7b3d024	Fix issue #2027 Remove localparam (#2137)	2024-05-21 12:13:46 +02:00
AEzzejjari	3cd458d03c	Modify AXI assertion and coverage model for easy utilization of WT and HPDcache (#2125)	2024-05-17 22:34:36 +02:00
JeanRochCoulon	4c58b50045	CV32A65X: Switch from WT to HPDCache (#2097) ... * switch from WT to HPDCache for CV32A65X configuration * Comment AXI agent asserts which are not compatible with HPDCache	2024-05-15 07:37:40 +00:00
JeanRochCoulon	dd763b4f4c	Rename FpuEn into RVF (#2109)	2024-05-15 09:16:44 +02:00
MarioOpenHWGroup	8a9d7a832b	Fix RVFI always_ff blocks (#2053)	2024-04-18 10:06:34 +02:00
JeanRochCoulon	e1ee77e02d	define WtDcacheWbufDepth as cva6 parameter and fix rvfi.svh (#2040)	2024-04-15 15:05:30 +02:00
Jalali	bfff84eaeb	Fix issue #2018 (#2023)	2024-04-09 17:43:21 +02:00
CoralieAllioux	de2e254cd4	[Xcelium support] Remove void from DPI definition (#1856)	2024-03-22 17:07:06 +01:00
MarioOpenHWGroup	62bdf11594	Bump core-v-verif d94f0de and fix questa simulator (#1915)	2024-03-21 19:02:41 +01:00
Côme	bd4b57cc64	Parametrization step 3 part 3 (last) (#1940)	2024-03-18 16:19:52 +01:00
Côme	4817575de9	Parametrization step 3 part 2 (#1939)	2024-03-18 12:06:55 +01:00
Côme	83d94bbb69	transform rvfi types into macros (#1921)	2024-03-12 17:34:27 +01:00
Côme	13dfa744d2	Parametrization step 1 (#1896)	2024-03-06 17:02:55 +01:00
Jalali	ce0ab81630	Connect CSRs info from RVFI_CSR in the testbench & update simulation target (#1879)	2024-02-28 16:20:24 +01:00
Yannick Casamatta	1dec79464e	add csr in rvfi (#1833)	2024-02-24 00:10:23 +01:00
AEzzejjari	5e80c104c9	AXI agent: Connect the the new AXI agent (#1817)	2024-02-18 23:31:44 +01:00
Jalali	3d7e417bce	Functional coverage : Add cross to illegal and exception coverage models (#1839)	2024-02-18 23:30:11 +01:00
MarioOpenHWGroup	c7f0eaf0d8	Bump verif/core-v-verif from fd68dfd to c7d2077 (#1828)	2024-02-13 14:20:21 +01:00
Yannick Casamatta	0ce6b40b26	Remove all logic and sequential related to RVFI in CORE cva6 (#1762)	2024-01-18 22:51:10 +01:00
Guillaume Chauvon	969c91eefa	Check that loaded elf segment does not overlap on last loaded address (#1755)	2024-01-11 11:37:00 +01:00
MarioOpenHWGroup	e5a0993ef9	Verilator Tandem Support (#1702)	2023-12-12 18:49:49 +01:00
MarioOpenHWGroup	220f534b6d	Spike Tandem Implementation using VCS simulator (#1561)	2023-11-09 19:29:24 +01:00
Cesar Fuguet	7de1345291	Add the HPDcache as cache subsystem (#1513) ... Add the HPDcache as another alternative for the cache subsystem. The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.	2023-10-16 09:26:20 +02:00
Florian Zaruba	93782ddfb5	Merge CVA6Cfg and ArianeCfg (#1321)	2023-09-28 11:41:38 +02:00
AEzzejjari	59863becc7	Code_Coverage: Exclude coverage of assertions, FSM, toggle of internal signals and constants (#1450)	2023-09-19 17:59:01 +02:00
Jean-Roch Coulon	b13530ccbc	fix regress tests and makefiles ... Co-authored-by: Côme Allart <come.allart@thalesgroup.com>	2023-09-07 11:38:34 +02:00
Côme Allart	736be43a73	move files to a verif directory	2023-09-07 09:50:50 +02:00