Andreas Traber
0cb4f2620c
Save unaligned rdata already in fifo, so that it only consumes one word instead of two
2015-11-30 15:50:03 +01:00
Andreas Traber
371a211be7
Fix bugs introduced in the last two commits
2015-11-30 15:13:08 +01:00
Andreas Traber
965be8059a
Move unalignment selection into prefetch buffer
2015-11-30 14:09:51 +01:00
Andreas Traber
5de1132e47
Make prefetch buffer FIFO a bit smarter, should cut one mux
2015-11-30 13:29:04 +01:00
Andreas Traber
b79a2f48c0
Simplify assignments in if stage a tiny little bit
2015-11-30 13:20:05 +01:00
Andreas Traber
ca79740744
Make register file conform to normal naming convention
2015-11-27 18:12:19 +01:00
Andreas Traber
45ceee59f7
Fixed issue that hardware loops with same endpoint did not work
2015-11-27 11:25:28 +01:00
Andreas Traber
116379e098
Fix instruction tracing, removed collision between custom* and our opcodes
2015-11-27 10:54:37 +01:00
Andreas Traber
4e02286710
Remove branch_req_Q signal, no need for it anymore :-)
2015-11-23 16:53:49 +01:00
Andreas Traber
1673d3f62a
Make sure branches are only done once
2015-11-23 16:51:06 +01:00
Andreas Traber
81a5e04a62
Make sure there are no two branches that are taken back-to-back
2015-11-23 16:41:57 +01:00
Andreas Traber
5da32ba5ec
This should fix most of the debug features
...
Basic test passes now, next step is to try and test it with an
interactive gdb
2015-11-19 14:17:07 +01:00
Andreas Traber
6ba66dc141
Rename mux select signals, allow for more aggressive optimizations in if
...
stage
2015-11-19 13:45:56 +01:00
Andreas Traber
e5bb1447cc
Cleanup hwloops, use parameters instead of defines, and also make it
...
completely generic
The only dependency that limits the number of hwloops now is the
encoding, the rest adapts automatically
2015-11-19 11:51:26 +01:00
Andreas Traber
b0a9e37c63
Fix hwloops, registers were stalled when they should have been active
2015-11-19 11:16:39 +01:00
Andreas Traber
89fec097fb
Cleanup branch signals, remove old signals that were no longer used
2015-11-19 10:53:12 +01:00
Andreas Traber
f5d408d7f4
Add an instr_valid_id signal to completely decouple the pipeline stages,
...
hopefully fixes the exception controller
2015-11-18 19:44:05 +01:00
Andreas Traber
4a166db65b
rename signals and try to make the whole thing a tiny bit faster
2015-11-18 19:44:05 +01:00
Andreas Traber
8a8b406a6c
Finally restyle the debug unit
2015-11-18 17:57:58 +01:00
Andreas Traber
cb73d88ed2
Fix a bug in the PCER CSR registers, it was not possible to activate more than the basic performance counter
2015-11-18 17:22:07 +01:00
Andreas Traber
c7cec664ac
Merge remote-tracking branch 'origin/master' into exc_ctrl
2015-11-17 10:36:15 +01:00
Sven Stucki
ec00ad8376
Add lp.setupi instruction
...
Hardware loops now have their own adder and no longer share it with the jump
target calculation.
The new lp.setupi instruction makes it possible to truly setup hardware loops
with a single instruction. For the lp.setup instruction, a register with the
counter had to be prepared first. The range of the new instruction is quite
limited though, it uses the shifted z-imm (5 bit, unsigned).
2015-11-03 17:44:17 +01:00
Sven Stucki
c001c323de
Change PULP custom opcodes
2015-11-03 15:38:23 +01:00
Sven Stucki
b99a8b90ba
Raise an illegal instruction exception for ecall/scall instructions.
...
Those instructions are no yet supported by the (exception) controller and have
been ignored until now. By causing an exception, they can at least be handled
in software if needed in the future.
2015-11-02 13:35:48 +01:00
Sven Stucki
286b82146c
Remove some spaces
2015-10-30 13:50:16 +01:00
Sven Stucki
98eb2cc044
Fix debug breakpoints and single-step with branches in ID
2015-10-29 14:12:50 +01:00
Sven Stucki
a770811ad4
Fix debug breakpoints (dbg_set_npc)
2015-10-29 14:01:53 +01:00
Sven Stucki
0fcdbf130f
Add test_en to register file clock gates
2015-10-28 12:47:33 +01:00
Andreas Traber
9532d68a71
Add test_en to core and propagate it to manual clock gates
...
Change line endings in register file to unix
2015-10-28 10:11:16 +01:00
Sven Stucki
82cf8ec258
Fix PPC/NPC tracking of debug unit
2015-10-27 18:31:49 +01:00
Sven Stucki
9efbaeba63
Add register for last branch PC
...
Needed in the debug unit, could be reused for precise exceptions.
2015-10-27 17:50:44 +01:00
Sven Stucki
05b44f97c0
Fix CSR access for debug unit
2015-10-27 17:18:31 +01:00
Sven Stucki
6773f4e3e1
Fix indentation in debug unit
2015-10-27 17:00:12 +01:00
Sven Stucki
d574cac20b
Fix problem with debug not working
2015-10-27 16:36:53 +01:00
Sven Stucki
c78a5a6954
Only read CSR when accessed
2015-10-27 14:15:09 +01:00
Sven Stucki
0b0b4c0c29
Fix performance counter access
2015-10-27 12:54:17 +01:00
Sven Stucki
bdb70cd4cc
Update compressed decoder to RVC 1.9
2015-10-27 12:39:59 +01:00
Andreas Traber
ad57e4effa
Only access CSR registers when we actually care about the rdata
...
This silences a warning in simulation and might also help for energy
consumption
2015-10-27 10:09:59 +01:00
Sven Stucki
b1862dd33a
Merge branch 'master' into exc_ctrl
2015-10-25 19:33:02 +01:00
Sven Stucki
f8dbb7ed92
Fix bug with hardware loops
2015-10-25 19:26:46 +01:00
Sven Stucki
9ee009a219
Fix exc controller ack not being sent
2015-10-23 16:49:16 +02:00
Sven Stucki
d2c8159a2d
Fix bug in csrrc instruction
2015-10-23 12:15:33 +02:00
Sven Stucki
3f6ba69413
Add first version of bad memory access exceptions
2015-10-22 13:20:43 +02:00
Sven Stucki
9f5beb527f
Fix comparison bug in ALU
2015-10-21 17:45:32 +02:00
Sven Stucki
459e34f747
Add error signals to LSU
2015-10-19 19:43:58 +02:00
Sven Stucki
906b51305e
Fix irq_enable
2015-10-19 19:42:10 +02:00
Sven Stucki
30318e694a
Fix interrupt not executed early enough after sleep
2015-10-19 19:42:10 +02:00
Sven Stucki
8d4c069d84
Fix exceptions during stalls
2015-10-19 19:42:10 +02:00
Sven Stucki
c28ca4444a
Fix exc wiring (not working yet)
2015-10-19 19:42:10 +02:00
Sven Stucki
c68a098059
Initial commit of updated exception controller
...
Largely untested, but should be wired up correctly.
2015-10-19 19:40:37 +02:00
