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Mono Color

• 4bf318ac63 GCC Shuffle2 Alignment Pasquale Davide Schiavone 2016-06-20 09:42:55 +02:00
• 11aa315721 Merge branch 'jalr-invalid-instruction' into 'master' Pasquale Davide Schiavone 2016-06-15 09:33:44 +02:00
• 840f500e79 Merge branch 'sv-packages' into 'master' Michael Gautschi 2016-06-13 16:27:13 +02:00
• 5a0ef29719 beautify banners Gautschi 2016-06-13 16:25:46 +02:00
• 7f8389cb40 Merge branch 'master' into 'sv-packages' Michael Gautschi 2016-06-13 16:17:00 +02:00
• 99da96f66b Trigger an invalid instruction if jalr op code bits 14:12 are not zero Robert Schilling 2016-06-13 14:37:19 +02:00
• d14327c1b8 fixes for new ipstools Francesco Conti 2016-06-09 19:37:09 +02:00
• 3277a983c7 Fixed misalignment memory access Pasquale Davide Schiavone 2016-06-07 14:19:56 +02:00
• 8a52246a00 moved to package based riscv core Gautschi 2016-06-03 14:04:44 +02:00
• 9031aa2398 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv Gautschi 2016-06-01 11:33:25 +02:00
• 59708f4422 fixed NCSIM simulation issue related to riscv_tracer Gautschi 2016-06-01 11:33:03 +02:00
• 4b70a0ffa0 Fixed vectorial comparison Pasquale Davide Schiavone 2016-05-30 12:12:07 +02:00
• 25a7705051 Fixed clip and clipu Pasquale Davide Schiavone 2016-05-25 17:20:59 +02:00
• ccdf02ecf8 Fixed pv.insert Pasquale Davide Schiavone 2016-05-19 15:20:52 +02:00
• 5bf76abb66 Fix new behaviour for clb Andreas Traber 2016-05-17 11:21:00 +02:00
• eab2d13bd2 Align ff1 and fl1 with the compiler builtins Andreas Traber 2016-05-13 18:22:59 +02:00
• 70968a1232 add pv.shuffleI1, pv.shuffleI2, pv.shuffleI3 instructions Andreas Traber 2016-05-13 16:20:32 +02:00
• b2591ce917 add an external resume signal for debug Andreas Traber 2016-05-12 12:22:16 +02:00
• b10a591c75 During first fetch, save PC from IF instead of ID Andreas Traber 2016-05-11 12:58:52 +02:00
• 4630c28884 New encoding, targeting Xpulpv2 now Andreas Traber 2016-05-10 17:45:57 +02:00
• d548ea579e Add sleeping bit to debug register Andreas Traber 2016-05-06 17:29:22 +02:00
• 7de2b84e44 Possibility to enter debug when never started yet Andreas Traber 2016-05-06 16:54:20 +02:00
• 3f53888355 Fix code style in debug_unit.sv Pasquale Davide Schiavone 2016-05-06 09:32:28 +02:00
• 66b51431bf for the moment being, deactivate tracing on FPGA Francesco Conti 2016-05-04 17:35:02 +02:00
• 1dca1ec78e Fix bug in the debug_unit Pasquale Davide Schiavone 2016-05-03 14:54:21 +02:00
• 3b766501af Merge branch_pc_ex and data_pc_ex, allow debugging during p.elw Andreas Traber 2016-05-02 13:47:13 +02:00
• 0b5f992952 Change address of GPR and NPC/PPC Andreas Traber 2016-04-29 17:11:23 +02:00
• a20c6e09c5 Allow debugging during sleep Andreas Traber 2016-04-29 16:19:44 +02:00
• 153c009090 Strip trailing whitespace Andreas Traber 2016-04-29 11:07:53 +02:00
• b227723ff5 Add all halt to core Andreas Traber 2016-04-29 10:56:25 +02:00
• cb97227440 Fix wfi + sleep in debug mode Pasquale Davide Schiavone 2016-04-29 10:23:25 +02:00
• df014ec3ba Fix issue #1 on github, byte address should always be 0 Andreas Traber 2016-04-26 16:56:42 +02:00
• 101ef713f1 Update core_id and cluster_id widths everywhere Andreas Traber 2016-04-21 18:32:35 +02:00
• 52a6c2002e Change size of core and cluster id Andreas Traber 2016-04-21 16:33:27 +02:00
• 1284e315ec Some fixes to debug Andreas Traber 2016-04-21 15:59:10 +02:00
• 57b77ba394 Fix some smallish issues Andreas Traber 2016-04-20 14:17:09 +02:00
• 5e30493243 Started work on MMIO debug Andreas Traber 2016-04-20 10:49:48 +02:00
• 74fed0d5ea Rearrange signed mode for mulhsu Andreas Traber 2016-04-13 17:28:37 +02:00
• cf5815a5e6 Fix a small bug in the short multiplier Andreas Traber 2016-04-13 16:10:05 +02:00
• d521ff3857 Also support mulhsu, so now we have the full set of the M extension Andreas Traber 2016-04-13 15:16:56 +02:00
• 4cae220197 Add support for mulhu as well Andreas Traber 2016-04-13 14:12:53 +02:00
• 5839e120bd Basic mulh implementation in 4 cycles Andreas Traber 2016-04-13 12:40:56 +02:00
• 3a96261dac Bit of beautify Andreas Traber 2016-04-12 11:11:45 +02:00
• 9278b0ebd0 Silence unique warnings by either adding defaults or removing unique where unnecessary Andreas Traber 2016-04-11 16:09:26 +02:00
• e899af4395 Fix syntax error for RTL compiler Andreas Traber 2016-04-06 17:47:29 +02:00
• 98d353806c integrate ext[hb][sz] into shuffle pack data path Andreas Traber 2016-04-06 09:32:52 +02:00
• a6976b443b Add proper targets for sub-ips Andreas Traber 2016-04-01 13:41:31 +02:00
• 8edb42244b Fix a compressed instruction decoding error Andreas Traber 2016-04-01 10:57:25 +02:00
• 1f2659d380 Linting Andy Traber 2016-03-31 17:33:04 +02:00
• 6ee9f3fe92 Fix wrong ordering of instructions in tracer in some cases Andreas Traber 2016-03-31 10:32:19 +02:00
• c786516d6c Add p.elw to tracer Andreas Traber 2016-03-31 09:38:52 +02:00
• d06042d7b1 Fix some synthesis warnings Andreas Traber 2016-03-30 13:27:06 +02:00
• 3859f66a1e Disable simulation checker again.. i should really take care of this Andreas Traber 2016-03-24 18:15:33 +01:00
• 68afee79a6 Added support for dot product Andreas Traber 2016-03-24 17:55:20 +01:00
• aa28fac157 Fix a nasty L0 buffer bug that happens with hardware loops Andreas Traber 2016-03-24 17:54:55 +01:00
• 1f2eef7606 Disabled simchecker per default again Andreas Traber 2016-03-23 13:38:00 +01:00
• a45273acc6 Added support for p.add[u][R]N Andreas Traber 2016-03-23 13:34:00 +01:00
• 8cf1e0e845 Add support for the clip operation Andreas Traber 2016-03-17 17:42:11 +01:00
• 99f7a2c50b Shuffle pack seems good after testShufflePack passes Andreas Traber 2016-03-17 12:48:57 +01:00
• b55241e3da Add TB for serial divider Andreas Traber 2016-03-16 18:53:21 +01:00
• b35c431632 Add alu_div also to src_files Andreas Traber 2016-03-16 16:33:51 +01:00
• 41dc5f3aa0 New version of divider, variable latency and thus faster on average Andreas Traber 2016-03-15 17:42:16 +01:00
• 4401708fdb Add preliminary version of shuffle/pack Andreas Traber 2016-03-15 13:27:12 +01:00
• d1db668404 Different optimizations in the ALU to make it smaller Andreas Traber 2016-03-11 17:10:57 +01:00
• 28b5a8e8dc Remove final mux for divider (costs one cycle) and always subtract Andreas Traber 2016-03-11 13:56:29 +01:00
• e8cc64fda6 First version of bit-serial divider Andreas Traber 2016-03-10 15:45:56 +01:00
• 47b713fd0d Add vector instructions to simulation tracer Andreas Traber 2016-03-03 13:34:58 +01:00
• 96e6eb82d9 We should also active the WE for vectorial instructions... Andreas Traber 2016-03-03 13:14:39 +01:00
• 7e07801be1 Switch bclr and bset instructions to comply with spec Andreas Traber 2016-03-03 10:56:00 +01:00
• 4ff7d58f02 Comment simchecker, should not be enabled per default Andreas Traber 2016-03-02 17:04:29 +01:00
• 4e587ececf Make sure that core_busy signal knows about the new data event load Andreas Traber 2016-03-02 15:33:46 +01:00
• 217adf9dc0 Add special event load instruction (p.elw) Andreas Traber 2016-03-02 14:26:29 +01:00
• 3b127ca326 Added support for pv.insert, pv.extract and pv.extractu Andreas Traber 2016-03-02 14:04:07 +01:00
• 09d6de8e42 Fixed vector opcode and added vectorial shifts Andreas Traber 2016-03-02 13:17:40 +01:00
• 9319fc71c1 Added min/max/abs support Andreas Traber 2016-03-02 11:15:32 +01:00
• 06144c2fbe Added partitioned adder for vectorial operations Andreas Traber 2016-03-02 11:01:35 +01:00
• 3495998840 Added vectorial comparisons and started decoding the rest of the vectorial operations, still needs testing though Andreas Traber 2016-03-02 10:11:48 +01:00
• 4efa86705c Added pv.ball instruction Andreas Traber 2016-02-25 14:21:50 +01:00
• e423b2c197 Added p.extract, p.extractu, p.insert, p.bclr, p.bset instructions Andreas Traber 2016-02-25 12:22:41 +01:00
• f436596e6f fixed src_files.yml Francesco Conti 2016-02-18 21:00:38 +01:00
• cc82192e45 Make sure the prefetcher works with any kind of stalls on data and instruction RAM access Andreas Traber 2016-02-19 10:41:55 +01:00
• f46dbaefad Fix two issues when the core is not getting the grant immediatly after sending the request Andreas Traber 2016-02-18 10:15:45 +01:00
• 50ee8b6ef5 Move riscv_tracer to different sub ip in src_files Andreas Traber 2016-02-17 18:22:02 +01:00
• d5a262cf24 fixed src_files.yml Francesco Conti 2016-02-17 14:50:03 +01:00
• 9858198ee5 Fix a bug in the LSU by making sure that branches can be finished correctly in the EX stage without impacting the WB stage Andreas Traber 2016-02-16 19:59:51 +01:00
• 18f5ffcd4a Fix wait_gnt signal for prefetcher if transaction was aborted Andreas Traber 2016-02-16 17:24:14 +01:00
• 656c391215 Respect jump done in controller for the eret instruction Andreas Traber 2016-02-16 17:21:24 +01:00
• 6b22441367 Fix handling of packed/unpacked structs in the riscv tracer Andreas Traber 2016-02-16 17:18:41 +01:00
• 2e7d74c8a6 moved src_files.txt to src_files.yml Francesco Conti 2016-02-11 16:41:29 +01:00
• 98a815fbc6 moved src_files.txt to src_files.yml Francesco Conti 2016-02-11 16:35:43 +01:00
• 9ecd6d9868 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv Francesco Conti 2016-02-11 16:14:50 +01:00
• c894ae0aec added FPGA-friendly register file to src_files.txt Francesco Conti 2016-02-11 16:07:09 +01:00
• a8987b5890 Added a basic description of the pipeline Andreas Traber 2016-02-11 15:58:29 +01:00
• 6f3358adfd Clarified hwloops with same endpoint Andreas Traber 2016-02-11 14:10:26 +01:00
• 918caba6f3 Update tracer and simchecker to be more verbose Andreas Traber 2016-02-11 13:47:04 +01:00
• 8c130d6398 Add README Andreas Traber 2016-02-10 17:25:56 +01:00
• 993e254947 Start adding interrupt support to simchecker Andreas Traber 2016-02-10 10:24:49 +01:00
• 33987fcc6c Handle boot address correctly Andreas Traber 2016-02-09 17:38:41 +01:00
• c39e27f3ac Allow nested interrupts and save current value of MSTATUS to MESTATUS upon entering an interrupt handler Andreas Traber 2016-02-09 09:21:26 +01:00
• d99c3c9f24 Simchecker now also supports rvc Andreas Traber 2016-02-08 13:08:56 +01:00