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Author SHA1 Message Date
Andreas Traber
463e74cf05 Only stall IF fsms when absolutely necessary 
This should take care of our synthesis issues (hopefully)
 2015-09-10 13:12:19 +02:00
Andreas Traber
847b652ce5 Change IF fifo depth to 3 to get performance from old IF back 2015-09-10 13:12:19 +02:00
Andreas Traber
db82a7ab8e Fix problem with unaligned compressed access 2015-09-10 13:12:19 +02:00
Andreas Traber
e0ea57968b Prefetcher basically done, works in pulpino without rvc 2015-09-10 13:12:19 +02:00
Andreas Traber
79bce5b31b Add a basic datasheet for RI5CY 
Not very detailed yet, needs a lot of work still
 2015-09-09 18:35:07 +02:00
Andreas Traber
b347299f31 Move compressed decoder/expander to IF stage 
I.e. the decoder is now before the IF/ID pipeline
It turns out there is enough timing budget to put it there and thus it
simplifies timing in the ID stage
 2015-09-08 19:33:10 +02:00
Sven Stucki
f5e1020f57 Add performance counter for compressed instructions 2015-09-08 17:24:39 +02:00
Andreas Traber
a330a8fe70 Improve inline comments in if_stage 2015-09-07 16:02:32 +02:00
Sven Stucki
216362365c Fix hwloop we 2015-09-07 11:53:21 +02:00
Sven Stucki
c2b519786b Merge branch 'hwloops' 2015-09-07 03:41:28 +02:00
Sven Stucki
b5aea15659 Finish hwloops addition 2015-09-07 03:40:28 +02:00
Sven Stucki
82afb4c839 Remove another unnecessary signal 2015-09-05 18:15:18 +02:00
Sven Stucki
24f0a588f5 More cleanup, remove unused signal 2015-09-05 16:33:51 +02:00
Sven Stucki
f9d0911329 Cleanup ID 2015-09-05 16:00:41 +02:00
Sven Stucki
a6dc8271e9 Wire up hwloops correctly, other small fixes 2015-09-05 03:37:50 +02:00
Andreas Traber
4f06b67e65 Simplify instr core interface 2015-09-04 15:52:35 +02:00
Andreas Traber
adb40aef43 Make instr_req_o signal dependent only on state 
=> removes ~1 gate from critical path and simplifies paths through i$
This will cost one cycle when waking up from sleep though :-/
 2015-09-04 13:54:19 +02:00
Sven Stucki
87e2eec128 Move hwloop regs into ID stage, WIP 2015-09-03 13:39:11 +02:00
Sven Stucki
77ef44a82f Separate jump target calculation from jump_in_id 2015-09-03 02:08:48 +02:00
Sven Stucki
2c2ad21c85 Reroute hwloops signals, fix counter mux 2015-09-02 18:32:03 +02:00
Sven Stucki
82eaaf86be Cleanup unneeded signals and dead code 2015-09-02 18:07:44 +02:00
Sven Stucki
e305a8e648 Harmonize indentation in controller 2015-09-02 17:11:23 +02:00
Sven Stucki
b81c7c6c57 Fix indentation in riscv_core.sv, better defaults 2015-09-02 16:31:16 +02:00
Andreas Traber
03a43245c7 Oops, fetch_addr_Q was multiply driven 2015-09-02 10:27:52 +02:00
Andreas Traber
3a7d4044e9 Fix width of irq_enable signal 2015-09-02 09:30:03 +02:00
Andreas Traber
ccb4497b36 Use 'x to simplify synthesis 2015-09-02 09:25:06 +02:00
Andreas Traber
5aa77089fa Move LSU related signals out of ex_stage and alu and put them inside LSU 2015-09-02 08:55:44 +02:00
Andreas Traber
a617bc496e Fix compile errors from last commit, fix synthesis warnigns and remove 
unused signals
 2015-09-02 08:38:25 +02:00
Sven Stucki
3a4ddb2af3 New CSR implementation, fix irq_enable signal 
Interrupts can now be switched on and off via CSR write, the current
status can be queried by a CSR read.

Pending interrupts still TBD.
 2015-09-02 01:39:07 +02:00
Andreas Traber
bb693c8e6b Add support to debug unit to set the Program Counter 2015-09-01 18:18:02 +02:00
Andreas Traber
68a9171fb3 Add missing branch instruction to compressed decoder 2015-09-01 17:24:12 +02:00
Andreas Traber
7e81d60510 Add two missing compressed instructions 2015-09-01 14:51:34 +02:00
Sven Stucki
bc51ae9305 Add sensible default in compressed decoder for one case 2015-09-01 12:58:49 +02:00
Andreas Traber
116b5f4641 Debug support: Make single-stepping work again 2015-09-01 12:55:26 +02:00
Andreas Traber
d5802e5e62 Simplified fetch logic a little bit 
This will probably not get us much performance though
 2015-09-01 09:53:03 +02:00
Andreas Traber
fbf8874e13 Simplify jump_target mux 
jump_target lies on the critical path of the instruction request path
 2015-09-01 08:47:31 +02:00
Sven Stucki
2c72b487dc Readd ALU flag to EX stage, use it for branch decision 2015-08-31 13:06:43 +02:00
Sven Stucki
4015362ee8 Remove TCDM_ADDR_PRECAL and some other cleanup 2015-08-31 12:35:26 +02:00
Sven Stucki
6aa40c336d Add hwloop decoding 2015-08-31 12:35:26 +02:00
Sven Stucki
5a38967a0c Cleanup space madness 2015-08-31 12:35:26 +02:00
Sven Stucki
5a821e643b Cosmetic changes in hwloop controller, ID and includes 2015-08-31 12:34:33 +02:00
Sven Stucki
6cdfde93c7 Fix hwloop code indentation 2015-08-31 12:33:27 +02:00
Sven Stucki
3c89d1400d Initial commit of OR10N hwloop controller and regs 2015-08-31 12:33:27 +02:00
Andreas Traber
387642f094 Fix WFI instruction 
It repeated instructions after it multiple times when not going to sleep
 2015-08-31 10:55:16 +02:00
Andreas Traber
b84dde00b8 Fix potential problem with core_busy_o, it is now also set when an 
instruction request is in flight and not only when we are decoding
 2015-08-31 10:24:39 +02:00
Andreas Traber
88b91c20c5 Rework pipeline flushes and exceptions 
WFI is working again, exception controller now only handles exceptions
(untested) and no flushes anymore
 2015-08-31 10:02:55 +02:00
Andreas Traber
dd57252f60 Improve display for illegal instructions 2015-08-31 09:16:03 +02:00
Sven Stucki
5f3b73ab8a Remove all case inside from decoder 2015-08-28 18:50:41 +02:00
Andreas Traber
2c93147fc3 Remove dead wb_stage file and module 2015-08-28 17:17:46 +02:00
Andreas Traber
1cbbcfb90b Fix linting errors/warnings and remove dead signals 
Part #2
 2015-08-28 17:15:55 +02:00